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1. 发明专利

JPS4818016B1 失效
公开(公告)号：JPS4818016B1
公开(公告)日：1973-06-02
申请号：JP5712568
申请日：1968-08-13
IPC分类号： H03M1/74 , H03K17/74 , H03K13/04

2. 发明专利

JPS4818014B1 失效
公开(公告)号：JPS4818014B1
公开(公告)日：1973-06-02
申请号：JP4753468
申请日：1968-07-09
IPC分类号： H03M1/66 , H03K13/04

3. 发明专利

JPS4843862A 失效
公开(公告)号：JPS4843862A
公开(公告)日：1973-06-25
申请号：JP9791372
申请日：1972-09-29
IPC分类号： H03M1/10 , H03M1/00 , H03K13/04

4. 发明专利

JPS4818017B1 失效
公开(公告)号：JPS4818017B1
公开(公告)日：1973-06-02
申请号：JP5712668
申请日：1968-08-13
IPC分类号： H03M1/74 , H03K17/74 , H03K13/04

5. 发明专利

FR2197276B1 未知
公开(公告)号：FR2197276B1
公开(公告)日：1977-02-18
申请号：FR7326631
申请日：1973-07-13
申请人： PERKIN ELMER CORP
IPC分类号： H03M1/74 , G06J1/00 , H03M1/00 , H03K13/04
摘要： A digital to analog converter includes a transformer having multiple sets of windings wherein each set comprises an ordered plurality of magnetically flux linked windings. Each of the windings of a set corresponds to a digit of a digital number of selected base and each of the sets includes a winding common to the sets and to which an analog input potential is applied. A plurality of digitally control switching means are provided and are coupled to associated sets of windings for coupling portions of the windings of an associated set in series and for providing the sum of the voltages developed therein. The switching means are operated in response to electrical input signals occurring in digital form thereby providing multiple output signals which are directly proportional to the product of the analog input signal and each of the digital signals. In one arrangement, the windings of a set and switching means are intercoupled in a manner for providing a full complement of the output signal thereby enabling the use of inverting amplifiers.

6. 发明专利

SU489218A1 未知
公开(公告)号：SU489218A1
公开(公告)日：1975-10-25
申请号：SU1835925
申请日：1972-10-06
IPC分类号： H03M1/66 , H03K13/04

7. 发明专利

DD112868A1 未知
公开(公告)号：DD112868A1
公开(公告)日：1975-05-05
申请号：DD17973074
申请日：1974-07-05
IPC分类号： H03K13/04

8. 发明专利

PL77575B2 未知
公开(公告)号：PL77575B2
公开(公告)日：1975-04-30
申请号：PL15421572
申请日：1972-03-22
IPC分类号： H03K13/04

9. 发明专利

SU448591A1 未知
公开(公告)号：SU448591A1
公开(公告)日：1974-10-30
申请号：SU1856758
申请日：1972-12-12
IPC分类号： H03M1/10 , H03K13/04 , G06F5/02

10. 发明专利

GB1366872A WAVE FORM SYNTHESIZERS 未知
公开(公告)号：GB1366872A
公开(公告)日：1974-09-11
申请号：GB4943770
申请日：1970-10-15
申请人： MARCONI CO LTD
IPC分类号： G01S7/04 , H03M1/00 , H03K13/04
摘要： 1366872 Function generators; waveform generators MARCONI CO Ltd 26 Aug 1971 [15 Oct 1970] 49437/70 Headings G4G and G4H [Also in Division H4] An approximation to a sine wave is produced from a digital output by weighting and combining n equal-amplitude rectangular waveforms where n is 2 or more, the waveforms exhibiting respectively during a time 0 to # (e.g. over half the period of the resultant sine wave), changes in the same direction at times 0, #/2n, 2#/2n, 3#/2n...and changes in the opposite direction at times #, (#-#/2n), (#-2#/2n), (#-3#/2n) ... The drawings show the waveforms for n = 4 (Fig. 2) and the resultant stepped waveform (Fig. 3) which is produced when the waveforms are weighted according to the amplitudes shown and then combined. The stepped waveform may be expressed as a Fourier series which is given in the Specification. The waveforms may be synthesized in a logic circuit 4 (details not described) fed by the four most significant outputs of a 13-bit counter 2. The waveforms A, B, C, D are weighted by the resistance network R1, R2, R3, R4 and the resultant stepped waveform smoothed by a first order filter 6, R6, C1 and then by a second-order filter 7, R8, R9, C2, C3 which has a maximally-flat characteristic. A clock 1 drives two 13-stage counters 2, 3 the stages of the second counter 3 being fed from an encoder 14 which encodes the angular position of a rotating aerial 15. The outputs of counter 3 are connected to an AND gate 10 and, with the interposition of inverters 12, 13 connected to the two most significant stages, to a further AND gate 11. The second counter 3 is connected to be re-set by a third AND gate 8 having inputs fed from the outputs of the first counter 2. The outputs of AND gates 10, 11 actuate sampling switches 17, 19 which connect holding circuits 18, 20 to the output of the synthesizing circuit In order to prevent the counter 3 from being reset when any digit from the encoder 14 is changing, the least significant input to the counter is used to trigger a pulse generator 9 which emits a short pulse used to inhibit the gate 8.

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