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1. 发明专利

CA2761491A1 CONTROL SYSTEM AND NODE ADDRESS SETTING METHOD FOR CONTROL SYSTEM 未知
公开(公告)号：CA2761491A1
公开(公告)日：2012-06-15
申请号：CA2761491
申请日：2011-12-13
申请人： HITACHI LTD
发明人： ARIMA TOSHIHIRO , OHASHI AKIHIRO , SHIRAISHI MASAHIRO , YOSHIDA KATSUMI , OTANI TASUYUKI , KOBAYASHI EIJI
IPC分类号： G05B9/03 , H05K10/00
摘要： A control system having processing units for outputting control commands; a plurality of I/O devices for receiving the control commands and outputting the control commands to a controlled system; and duplicate intermediary units which relay the control commands from the processing units to the I/O devices, wherein each of the duplicate intermediary units includes an upper address setting device which generates upper address data and outputs the upper address data to the I/O devices; and each of the I/O devices includes an upper address comparator for comparing the received upper address data, an upper address setting unit for selecting upper address data on the basis of the result of comparison, and a line control unit for forming a node address for a particular I/O device by merging selected upper address data and lower address data determined by the particular I/O device.

2. 发明专利

CA2693033A1 FAULT DIAGNOSIS APPARATUS AND FAULT DIAGNOSIS METHOD OF MULTI-CHANNEL ANALOG INPUT/OUTPUT CIRCUIT 未知
公开(公告)号：CA2693033A1
公开(公告)日：2010-09-06
申请号：CA2693033
申请日：2010-02-16
申请人： HITACHI LTD
发明人： TERAE HISASHI , ISHIKAWA MASAKAZU , FURUTA YASUYUKI , YOSHIDA KATSUMI , NISHIOKA ATSUSHI , KIYOFUJI YASUHIRO , KASAHARA TAKENORI , NAGAYAMA SYUICHI , KAWAWA FUJIYA , KUBOTA MANABU , OOTANI TATSUYUKI , TANAKA HIDECHIYO
IPC分类号： G01R31/3161 , H03M1/10
摘要： A fault diagnosis apparatus and method capable of simultaneously detecting the fault of a multiplexer and the fault of an A/D converter and isolating and identifying causes of these faults, the multiplexer and the A/D converter being used in a multi-channel analog input/output circuit. Test-voltage values are inputted from a diagnosis-voltage input unit into the multiplexer and the A/D converter constituting an analog-signal conversion unit, the multiplexer having plural channels, the A/D converter converting outputs from the multiplexer into digital signals, the test-voltage values being different from each other for each channel of the multiplexer. Comparisons are made between the digital voltage values and the test-voltage values inputted, the digital voltage values being outputted for each channel of the multiplexer. From this comparison result, it is judged whether the multiplexer is at fault or the A/D converter is at fault.

3. 发明专利

CA2761491C CONTROL SYSTEM AND NODE ADDRESS SETTING METHOD FOR CONTROL SYSTEM 未知
公开(公告)号：CA2761491C
公开(公告)日：2015-09-08
申请号：CA2761491
申请日：2011-12-13
申请人： HITACHI LTD
发明人： ARIMA TOSHIHIRO , OHASHI AKIHIRO , SHIRAISHI MASAHIRO , YOSHIDA KATSUMI , OTANI TASUYUKI , KOBAYASHI EIJI
IPC分类号： G05B9/03 , H05K10/00
摘要： A control system having processing units for outputting control commands; a plurality of I/O devices for receiving the control commands and outputting the control commands to a controlled system; and duplicate intermediary units which relay the control commands from the processing units to the I/O devices, wherein each of the duplicate intermediary units includes an upper address setting device which generates upper address data and outputs the upper address data to the I/O devices; and each of the I/O devices includes an upper address comparator for comparing the received upper address data, an upper address setting unit for selecting upper address data on the basis of the result of comparison, and a line control unit for forming a node address for a particular I/O device by merging selected upper address data and lower address data determined by the particular I/O device.

4. 发明专利

CA2693033C FAULT DIAGNOSIS APPARATUS AND FAULT DIAGNOSIS METHOD OF MULTI-CHANNEL ANALOG INPUT/OUTPUT CIRCUIT 未知
公开(公告)号：CA2693033C
公开(公告)日：2014-10-14
申请号：CA2693033
申请日：2010-02-16
申请人： HITACHI LTD
发明人： TERAE HISASHI , ISHIKAWA MASAKAZU , FURUTA YASUYUKI , YOSHIDA KATSUMI , NISHIOKA ATSUSHI , KIYOFUJI YASUHIRO , KASAHARA TAKENORI , NAGAYAMA SYUICHI , KAWAWA FUJIYA , KUBOTA MANABU , OOTANI TATSUYUKI , TANAKA HIDECHIYO
IPC分类号： G01R31/3161 , H03M1/10
摘要： A fault diagnosis apparatus and method capable of simultaneously detecting the fault of a multiplexer and the fault of an A/D converter and isolating and identifying causes of these faults, the multiplexer and the A/D converter being used in a multi-channel analog input/output circuit. Test-voltage values are inputted from a diagnosis-voltage input unit into the multiplexer and the A/D converter constituting an analog-signal conversion unit, the multiplexer having plural channels, the A/D converter converting outputs from the multiplexer into digital signals, the test-voltage values being different from each other for each channel of the multiplexer. Comparisons are made between the digital voltage values and the test-voltage values inputted, the digital voltage values being outputted for each channel of the multiplexer. From this comparison result, it is judged whether the multiplexer is at fault or the A/D converter is at fault.

5. 发明专利

CA2743968A1 MULTI UNIT CONTROLLER 未知
公开(公告)号：CA2743968A1
公开(公告)日：2011-12-25
申请号：CA2743968
申请日：2011-06-22
申请人： HITACHI LTD
发明人： SUGIMOTO YUTA , NISHIOKA ATSUSHI , KOBAYASHI EIJI , OHASHI AKIHIRO , YOSHIDA KATSUMI , NAKAMURA SATOSHI , NEMOTO FUMIHIKO
IPC分类号： H01R25/00 , G05B99/00 , H01R13/629
摘要： A multi unit controller has a plurality of base units each of which includes a control unit connector, a base unit connector through which the base units juxtaposed to each other are connected to each other, and a plurality of control units connected to the base units respectively through the respective control unit connector, wherein the base units juxtaposed vertically.

6. 发明专利

CA2743968C MULTI UNIT CONTROLLER 未知
公开(公告)号：CA2743968C
公开(公告)日：2014-09-02
申请号：CA2743968
申请日：2011-06-22
申请人： HITACHI LTD
发明人： SUGIMOTO YUTA , NISHIOKA ATSUSHI , KOBAYASHI EIJI , OHASHI AKIHIRO , YOSHIDA KATSUMI , NAKAMURA SATOSHI , NEMOTO FUMIHIKO
IPC分类号： H01R25/00 , G05B99/00 , H01R13/629
摘要： A multi unit controller has a plurality of base units each of which includes a control unit connector, a base unit connector through which the base units juxtaposed to each other are connected to each other, and a plurality of control units connected to the base units respectively through the respective control unit connector, wherein the base units juxtaposed vertically.

7. 发明专利

JP2013182360A Hot line insertion/extraction device and hot line insertion/extraction method 有权
标题翻译：热线插入/提取装置和热线插入/提取方法
公开(公告)号：JP2013182360A
公开(公告)日：2013-09-12
申请号：JP2012044956
申请日：2012-03-01
申请人： Hitachi Ltd , 株式会社日立製作所 , Hitachi Information & Control Solutions Ltd , 株式会社日立情報制御ソリューションズ
发明人： ARIMA TOSHIHIRO , YOSHIDA KATSUMI , KUMAKURA KIKUYA , NAGAYAMA HISAO , NAGASHIMA HIRONORI
IPC分类号： G06F3/00
摘要： PROBLEM TO BE SOLVED: To prevent an input/output operation from being started in an incomplete connection state after the insertion of a hot line.SOLUTION: A hot line insertion/extraction device 1 controls the execution or stop of the input/output operation of information in the case of attaching/detaching a process input/output device 50 in a control system 100. Concretely, the hot line insertion/extraction device 1 includes: a switching part 11 for hot line insertion/extraction for switching the signal level of a switching part signal 142 by accepting the operation of a user; a reset part 12 for switching the signal level of a reset part signal 145 after the lapse of a predetermined time after the insertion of a hot line; an arithmetic part 14 for acquiring and calculating the signal level of the switching part signal 142 and the signal level of the reset part signal 145, and for outputting a hot line insertion/extraction signal 147 and a reset signal 148; and an input/output control part 13 for controlling the execution or stop of the input/output operation of information on the basis of the combination of the signal levels of the hot line insertion/extraction signal 147 and the reset signal 148.
摘要翻译：要解决的问题：在插入热线之后，防止输入/输出操作在不完全连接状态下启动。解决方案：热线插入/拔出装置1控制输入/输出操作的执行或停止具体地，热线插入/拔出装置1包括：用于热线插入/提取的切换部分11，用于切换信号电平的信号电平通过接受用户的操作来切换部分信号142; 复位部分12，用于在插入热线之后经过预定时间之后切换复位部分信号145的信号电平; 用于获取和计算切换部分信号142的信号电平和复位部分信号145的信号电平，并输出热线插入/提取信号147和复位信号148的算术部分14; 以及输入/输出控制部分13，用于基于热线插入/提取信号147和复位信号148的信号电平的组合来控制信息的输入/输出操作的执行或停止。

8. 发明专利

JP2015022401A 通信制御装置、通信制御方法及び通信制御システム有权
标题翻译：通信控制装置，通信控制方法和通信控制系统
公开(公告)号：JP2015022401A
公开(公告)日：2015-02-02
申请号：JP2013148441
申请日：2013-07-17
申请人：株式会社日立製作所 , Hitachi Ltd
发明人： IMAZAWA TAKAO , OTANI TATSUYUKI , YOSHIDA KATSUMI , TAYAMA HIROYUKI , NAGASHIMA HIRONORI , DOKEN TOMOHIKO
IPC分类号： G05B19/05 , G05B23/02
摘要：【課題】演算装置とプロセス入出力装置との間で伝送される入出力データの伝送単位を最適化する。【解決手段】演算装置1と複数のプロセス入出力装置31との間で互いに非同期にメモリ転写によるデータ伝送を行う通信制御装置2は、入出力データのデータサイズと前記通信制御装置に接続されている機器の構成情報とから前記演算装置とのデータ転送単位となるノードの数を決定するノード数決定部27と、前記演算装置と前記ノードを含む通信フレームを送受信する上流通信制御部21と、複数のプロセス入出力装置と前記入出力データを送受信する下流通信制御部24と、を備え、前記下流通信制御部は、複数のプロセス入力装置から受信した複数の入力データを前記ノード数決定部により決定された数のノードに統合し、前記上流通信制御部は、前記演算装置から受信した前記ノードに含まれる複数の出力データを、対応する複数のプロセス出力装置に展開する。【選択図】図1
摘要翻译：要解决的问题：优化在运算单元和过程输入/输出设备之间传输的输入/输出数据的传输单元。解决方案：通信控制设备2通过存储器传输在运算单元1之间彼此异步地进行数据传输多个处理输入/输出装置31.通信控制装置包括：节点编号确定单元27，根据输入/输出数据和配置的数据大小确定使用算术装置的数据传送单元的节点数与通信控制装置连接的装置的信息; 上行通信控制单元21，向包含运算装置的运算装置发送包含各节点的通信帧; 以及向/从多个处理输入/输出装置发送和接收输入/输出数据的下游通信控制单元24。下游通信控制单元将从多个处理输入设备接收的多条输入数据合并到由节点号确定单元确定的节点中。上游通信控制单元将包括在从运算单元接收的节点中的多个输出数据扩展到多个对应的处理输出设备。

9. 发明专利

JP2010212808A Device and method for diagnosis of fault in multi-channel analog input output circuit 有权
标题翻译：用于诊断多通道模拟输入输出电路故障的装置和方法
公开(公告)号：JP2010212808A
公开(公告)日：2010-09-24
申请号：JP2009054194
申请日：2009-03-06
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TERAE NAO , ISHIKAWA MASAKAZU , FURUTA YASUYUKI , YOSHIDA KATSUMI , NISHIOKA ATSUSHI , KIYOFUJI YASUHIRO , KASAHARA TAKENORI , NAGAYAMA SHUICHI , KAWAKAZU FUJIYA , KUBOTA MANABU , OTANI TATSUYUKI , TANAKA HIDECHIYO
IPC分类号： H03K17/00 , G01R31/316 , H03M1/10
CPC分类号： G05B19/0425 , G05B2219/21137 , G05B2219/24069 , G05B2219/25435
摘要： PROBLEM TO BE SOLVED: To provide a device and method for diagnosis of a fault capable of simultaneously detecting the fault of a multiplexer used for a multi-channel analog input-output circuit and the fault of an A/D converter, and classifying the causes of the faults.
SOLUTION: A diagnosis voltage input unit inputs test voltage values different per channel of a multiplexer to the multiplexer having a plurality of channels configuring an analog signal conversion unit and to the A/D converter for converting the output of the multiplexer into a digital signal. Then, a digital voltage value output per channel is compared with the input test voltage value to determine whether a fault is in the multiplexer or the A/D converter on the basis of results of comparison.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供用于诊断能够同时检测用于多通道模拟输入 - 输出电路的多路复用器的故障和A / D转换器的故障的故障的装置和方法，以及分类故障原因。解决方案：诊断电压输入单元将具有多路复用器的每个通道不同的测试电压值输入到具有构成模拟信号转换单元的多个通道的复用器和用于将多路复用器的输出转换成A / 数字信号。然后，将每个通道的数字电压值输出与输入的测试电压值进行比较，以根据比较结果确定故障是在多路复用器还是A / D转换器中。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JPH01211170A POS TERMINAL EQUIPMENT 失效
公开(公告)号：JPH01211170A
公开(公告)日：1989-08-24
申请号：JP3688388
申请日：1988-02-19
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： ISHIKAWA TORU , TAKAHASHI TORU , SHIBATA YOSUKE , YOSHIDA KATSUMI
IPC分类号： G07G1/12 , G06K17/00
摘要： PURPOSE:To simplify register business by setting a value, whose fraction is dropped or raised, at a claimed amount, and writing the dropped or raised fraction amount into a recording medium as the residual fraction amount of a next transaction. CONSTITUTION:Before the start of the commodity registration of a customer, by reading a magnetic card 30 possessed by the customer, a residual fraction amount 32 (X) recorded on the card 30 i set at a last residual fraction amount buffer 23. At the time of the completion of the commodity registration, the total amount (Y) of purchased commodities is set at a purchased total amount buffer 24. Here, the residual fraction amount X is subtracted from the purchased total amount Y, and its result (Z) is set at a temporary buffer 25. Next, according to the number of fraction digits set at a fraction digit number presetting area 26 beforehand, the value Z of the fraction amount is raised, its result is set at a claimed amount buffer 21 as a claimed amount (P), and a raised fraction amount (Q) is set at a present residual fraction amount buffer 22. Further, the fraction amount Q is written on the card 30.

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