专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

DE69530155T2 未知
公开(公告)号：DE69530155T2
公开(公告)日：2004-01-15
申请号：DE69530155
申请日：1995-09-12
申请人： HITACHI LTD
发明人： MORI MUTSUHIRO , YASUDA YASUMICHI , HOSOYA HIROMI
IPC分类号： H01L29/41 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/749 , H01L29/78 , H01L29/861 , H02M7/538
摘要： The high voltage semiconductor device is provided with a p layer (13) which forms a main pn- junction, a plurality of p layers (131-135) which surround the p layer (13) in a ring form, a ring-like n+ layer (14) which further surrounds those p layers, forward field plates extending in the peripheral direction and reverse field plates extending in the inside direction, the field plates being in contact at a low resistance with the p and n+ layers (13, 131-135, 13) and reaching the surface of an n- layer (12) through an insulating film (30), the area of the field plates being not less than one half of the n- surface. The present invention is effective in stabilizing the blocking voltage of a high voltage semiconductor device which is used in a severe environment, and is very effective in improving the reliability of a high voltage control unit.

2. 发明专利

DE3852444T2 未知
公开(公告)号：DE3852444T2
公开(公告)日：1995-05-04
申请号：DE3852444
申请日：1988-08-22
申请人： HITACHI LTD
发明人： MORI MUTSUHIRO , TANAKA TOMOYUKI , YASUDA YASUMICHI , NAKANO YASUNORI
IPC分类号： H01L29/68 , H01L21/225 , H01L21/331 , H01L21/336 , H01L29/739 , H01L29/78 , H01L21/28 , H01L29/08 , H01L29/72
摘要： An insulated gate semiconductor device comprises: a semiconductor substrate having a first semiconductor region (11) on one surface, a second semiconductor region (12) of a second conductivity type v adjacent to said first semiconductor region on the other surface, a plurality of third semiconductor regions (13) of the first conductivity type extending into said second semiconductor region, two fourth (14) semiconductor regions, of the second conductivity type, extending into each of said third semiconductor regions, and a plurality of insulating gates (21, 22, 31) formed on the other of the pair of main surfaces, wherein a length (B) of each of said insulating gates, from one side to another opposed side of each insulating gate, is longer than a distance (A) between adjacent sides of adjacent insulating gates.

3. 发明专利

DE69318239D1 未知
公开(公告)号：DE69318239D1
公开(公告)日：1998-06-04
申请号：DE69318239
申请日：1993-09-15
申请人： HITACHI LTD
发明人： KOBAYASHI HIDEO , MORI MUTSUHIRO , YASUDA YASUMICHI , NAKANO YASUNORI
IPC分类号： H01L29/78 , H01L21/331 , H01L21/8222 , H01L27/06 , H01L29/06 , H01L29/40 , H01L29/73 , H01L29/732 , H01L29/74 , H01L29/861 , H02P27/06
摘要： A highly reliable semiconductor device having a planar junction, which comprises a main junction and a plurality of field limiting ring regions (1031 - 1037) surrounding the main junction, and an electrically floating conduction layer (18) to completely cover the surface of an n layer between the main junction and the nearest field limiting ring region (1031) thereto through an insulating layer (15) can suppress influences by external factors such as charged particles, etc., e.g. when a voltage of making the main junction into a reverse bias state is applied, the potential of the conduction layer is fixed to an intermediate potential between the main junction and the nearest field limiting ring region thereto and plays a role of shield effect, and even if the device is incorporated into a resin-sealed package and subjected to reliability tests (high temperature DC reverse bias tests), the breakdown voltage is not changed at all.

4. 发明专利

DE3852444D1 未知
公开(公告)号：DE3852444D1
公开(公告)日：1995-01-26
申请号：DE3852444
申请日：1988-08-22
申请人： HITACHI LTD
发明人： MORI MUTSUHIRO , TANAKA TOMOYUKI , YASUDA YASUMICHI , NAKANO YASUNORI
IPC分类号： H01L29/68 , H01L21/225 , H01L21/331 , H01L21/336 , H01L29/739 , H01L29/78 , H01L21/28 , H01L29/08 , H01L29/72
摘要： An insulated gate semiconductor device comprises: a semiconductor substrate having a first semiconductor region (11) on one surface, a second semiconductor region (12) of a second conductivity type v adjacent to said first semiconductor region on the other surface, a plurality of third semiconductor regions (13) of the first conductivity type extending into said second semiconductor region, two fourth (14) semiconductor regions, of the second conductivity type, extending into each of said third semiconductor regions, and a plurality of insulating gates (21, 22, 31) formed on the other of the pair of main surfaces, wherein a length (B) of each of said insulating gates, from one side to another opposed side of each insulating gate, is longer than a distance (A) between adjacent sides of adjacent insulating gates.

5. 发明专利

DE3787763D1 未知
公开(公告)号：DE3787763D1
公开(公告)日：1993-11-18
申请号：DE3787763
申请日：1987-07-13
申请人： HITACHI LTD
发明人： MORI MUTSUHIRO , TANAKA TOMOYUKI , YASUDA YASUMICHI
IPC分类号： H01L27/06 , H01L21/8249 , H01L27/07 , H01L29/73 , H01L29/68
摘要： Disclosed is a composite semiconductor device which comprises: a second and a third semiconductor regions (2l, 22) of a second conductivity type formed in a first semiconductor region (l2) of a first conductivity type independently of each other and so as to be exposed on one main surface of a semiconductor substrate (ll); a fourth and a fifth semiconductor regions (3l, 32) of the first conductivity type formed in the second semiconductor region (2l) independently of each other and so as to be exposed on the one main surface of the semiconductor substrate; a first insulated gate electrode (54) formed on the second semiconductor region (2l) located between the fifth and first semiconductor regions (32, l2) and exposed on the one main surface; a second insulated gate electrode (54) formed on the first semiconductor region (l2) located between the second and third semiconductor regions (2l, 22) and exposed on the one main surface; an electrode (52, 55) which shorts the fourth and third semiconductor regions (3l, 22); another electrode (53) which shorts the second and fifth semiconductor regions (2l, 32); and a further electrode (5l) provided in the first semiconductor region (l2).

6. 发明专利

DE68904343D1 未知
公开(公告)号：DE68904343D1
公开(公告)日：1993-02-25
申请号：DE68904343
申请日：1989-04-03
申请人： HITACHI LTD
发明人： SAKURAI NAOKI , MORI MUTSUHIRO , TANAKA TOMOYUKI , YASUDA YASUMICHI , NAKANO YASUNORI , YATSUO TSUTOMU
IPC分类号： H01L29/68 , H01L21/76 , H01L29/08 , H01L29/739 , H01L29/78 , H01L29/72

7. 发明专利

CA1279409C COMPOSITE SEMICONDUCTOR DEVICE 未知
公开(公告)号：CA1279409C
公开(公告)日：1991-01-22
申请号：CA542081
申请日：1987-07-13
申请人： HITACHI LTD
发明人： MORI MUTSUHIRO , TANAKA TOMOYUKI , YASUDA YASUMICHI
IPC分类号： H01L27/06 , H01L21/8249 , H01L27/07 , H01L29/73 , H01L29/68
摘要： Disclosed is a composite semiconductor device which comprises: a second and a third semiconductor regions of a second conductivity type formed in a first semiconductor region of a first conductivity type independently of each other and so as to be exposed on one main surface of a semiconductor substrate; a fourth and a fifth semiconductor regions of the first conductivity type formed in the second semiconductor region independently of each other and so as to be exposed on the one main surface of the semiconductor substrate; a first insulated gate electrode formed on the second semiconductor region located between the fifth and first semiconductor regions and exposed on the one main surface; a second insulated gate electrode formed on the first semiconductor region located between the second and third semiconductor regions and exposed on the one main surface; an electrode which shorts the fourth and third semiconductor regions; another electrode which shorts the second and fifth semiconductor regions; and a further electrode provided in the first semiconductor region.

8. 发明专利

DE3381606D1 未知
公开(公告)号：DE3381606D1
公开(公告)日：1990-06-28
申请号：DE3381606
申请日：1983-02-18
申请人： HITACHI LTD
发明人： TANAKA TOMOYUKI , YAMADA KOICHIRO , YASUDA YASUMICHI
IPC分类号： H01L21/314 , H01L21/3215 , H01L21/331 , H01L29/04 , H01L29/08 , H01L29/72 , H01L29/167
摘要： Semiconductor device having a hetero junction in which a polycrystalline or amorphous silicon layer (7) doped with oxygen is formed over a monocrystalline silicon semiconductor substrate (1) as a passivation film, and impurities are doped only into the desired portions of the layer (7), thereby forming a semiconductor layer having a desired conductivity type. The photoetching step which is heretofore required can be omitted by forming the oxygen-doped polycrystalline or amorphous silicon layer (7) and then doping impurities having the desired conductive type.

9. 发明专利

DE69530155D1 未知
公开(公告)号：DE69530155D1
公开(公告)日：2003-05-08
申请号：DE69530155
申请日：1995-09-12
申请人： HITACHI LTD
发明人： MORI MUTSUHIRO , YASUDA YASUMICHI , HOSOYA HIROMI
IPC分类号： H01L29/41 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/749 , H01L29/78 , H01L29/861 , H02M7/538
摘要： The high voltage semiconductor device is provided with a p layer (13) which forms a main pn- junction, a plurality of p layers (131-135) which surround the p layer (13) in a ring form, a ring-like n+ layer (14) which further surrounds those p layers, forward field plates extending in the peripheral direction and reverse field plates extending in the inside direction, the field plates being in contact at a low resistance with the p and n+ layers (13, 131-135, 13) and reaching the surface of an n- layer (12) through an insulating film (30), the area of the field plates being not less than one half of the n- surface. The present invention is effective in stabilizing the blocking voltage of a high voltage semiconductor device which is used in a severe environment, and is very effective in improving the reliability of a high voltage control unit.

10. 发明专利

DE3856084T2 未知
公开(公告)号：DE3856084T2
公开(公告)日：1998-08-27
申请号：DE3856084
申请日：1988-08-22
申请人： HITACHI LTD
发明人： MORI MUTSUHIRO , TANAKA TOMOYUKI , YASUDA YASUMICHI , NAKANO YASUNORI
IPC分类号： H01L29/68 , H01L21/225 , H01L21/331 , H01L21/336 , H01L29/739 , H01L29/78 , H01L29/772 , H01L29/72
摘要： An insulated gate semiconductor device comprises: a semiconductor substrate having a first semiconductor region (11) on one surface, a second semiconductor region (12) of a second conductivity type v adjacent to said first semiconductor region on the other surface, a plurality of third semiconductor regions (13) of the first conductivity type extending into said second semiconductor region, two fourth (14) semiconductor regions, of the second conductivity type, extending into each of said third semiconductor regions, and a plurality of insulating gates (21, 22, 31) formed on the other of the pair of main surfaces, wherein a length (B) of each of said insulating gates, from one side to another opposed side of each insulating gate, is longer than a distance (A) between adjacent sides of adjacent insulating gates.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式