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1. 发明专利

DE69521159D1 未知
公开(公告)号：DE69521159D1
公开(公告)日：2001-07-12
申请号：DE69521159
申请日：1995-02-23
申请人： HITACHI LTD
发明人： HONJO SHIGERU , YANAGISAWA KAZUMASA , INOUE KIYOSHI
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8246 , H01L27/10 , H01L27/105

2. 发明专利

DE69521159T2 未知
公开(公告)号：DE69521159T2
公开(公告)日：2002-02-28
申请号：DE69521159
申请日：1995-02-23
申请人： HITACHI LTD
发明人： HONJO SHIGERU , YANAGISAWA KAZUMASA , INOUE KIYOSHI
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8246 , H01L27/10 , H01L27/105

3. 发明专利

JPH0997494A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH0997494A
公开(公告)日：1997-04-08
申请号：JP9820296
申请日：1996-04-19
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HANAMURA SHOJI , MINATO OSAMU , HONJO SHIGERU , MASUHARA TOSHIAKI , MORIWAKI NOBUYUKI , KOJIMA FUMIO
IPC分类号： G11C11/401 , G11C11/406
摘要： PROBLEM TO BE SOLVED: To extremely reduce the power consumption at the time of refresh operation in a non-selection state of a chi and to enable battery backup at the time of refresh operation, in a semiconductor memory device using a volatile memory cell. SOLUTION: At the time of refresh operation, word line division control means 13, 13' control a word line division means 5 so that the word line division means 5 selects corresponding to a signal of a main word line 6 independently of a decoding signal. At the time of reading and writing information, the work line division control means 13, 13' control a word line division means 5 so that the word line division means 5 selects division word lines 7, 7' responding the corresponding to the decoding signal and the signal of a main word line 6.

4. 发明专利

JPH07263578A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07263578A
公开(公告)日：1995-10-13
申请号：JP5849095
申请日：1995-03-17
申请人： HITACHI LTD
发明人： HONJO SHIGERU , MINATO OSAMU , SAKAI YOSHIO , YAMANAKA TOSHIAKI , SHIMOHIGASHI KATSUHIRO , MASUHARA TOSHIAKI
IPC分类号： H01L27/11 , H01L21/8244
摘要： PURPOSE:To provide a semiconductor memory device which is unlikely to cause soft errors by forming a new capacitor different from a parasitic capacitor of the effective region of a resistive element forming a memory cell and a polycrystalline silicon and a polycrystalline silicon layer oppositely disposed through an insulating film to increase a stored electric charge quantity. CONSTITUTION:Insulating separation layers 19 to 21 are provided within a p-type substrate 18, and an n-channel type MOST34 with n-type impurity layers 22, 23 for a drain and a source and a gate 26 and an n-channel type MOST35 with a gate 27 are formed. After that, a storage capacity is formed in the upper part of the MOSTs34, 35 by holding an insulating material 29 between storage nodes 23, 27 and a second-layer polysilicon layer 30. After an insulating material layer 32 is formed thereon, a load resistor is formed of a third-layer polysilicon layer 33. Thereby, a static memory cell of small occupation area capable of realizing a large-capacitance static RAM can be obtained.

5. 发明专利

JPH065081A STATIC RAM 失效
公开(公告)号：JPH065081A
公开(公告)日：1994-01-14
申请号：JP18610692
申请日：1992-06-19
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR , HITACHI TOBU SEMICONDUCTOR LTD
发明人： HONJO SHIGERU , OGURA KAZUTOMO , SHIRASAWA TAKAYUKI , MOMII MASATO , TAMAI HIROSHI
IPC分类号： G11C11/413 , G11C11/401 , G11C11/407 , G11C11/41 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To stabilize the write operation of the title RAM and to increase the memory capacity of the title RAM by a method wherein a complementary data-line selection circuit which collectively selects a plurality of mutually adjacent complementary data lines is installed and each pitch between the plurality of complementary data lines is made wider. CONSTITUTION:Each pitch P1 between inverted data lines B for complementary data lines D7 having an address Y0 and noninverted data lines T for complementary data lines D0 having an address Y1 is made wider than each pitch T2 between complementary data lines to which the same address has been allocated. When the pitch P1 between the adjacent data lines is constituted to be wide in a Y-address unit in this manner, a parasitic capacity can be reduced between the complementary data lines, and the information holding operation of a memory cell is maintained. On the other hand, even when the P2 between the adjacent data lines for data lines D0 to D7 is made narrower than the P1, no problem is caused because an impedance is low. Thereby, many memory cells can be connected, and it is possible to prevent that nonselection memory cells are written erroneously even when a write operation is performed at a large signal amplitude.

6. 发明专利

JPH02148852A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH02148852A
公开(公告)日：1990-06-07
申请号：JP30106888
申请日：1988-11-30
申请人： HITACHI LTD
发明人： HONJO SHIGERU , SASAKI KATSURO , ISHIBASHI KOICHIRO , AOKI MASAAKI , SHIMOHIGASHI KATSUHIRO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238 , H01L21/8242 , H01L21/8244 , H01L27/092 , H01L27/10 , H01L27/108 , H01L27/11
摘要： PURPOSE:To prevent decrease in threshold voltage and in breakdown strength between a source and a drain and to suppress leak currents to the side of a substrate by providing impurity-doped region whose impurity concentration is higher than the impurity concentration of the semiconductor substrate and which has the same conductivity type as that of the substrate directly beneath a gate electrode at a specified depth, and setting the position of the peak of the impurity concentration within a specified distance from the surface of the substrate. CONSTITUTION:An n-type impurity layer 10' and a p-type impurity layer 10 are provided in an n-type protruding region 13' and a p-type protruding region 12' directly beneath gate electrodes 16 of p-type and n-type transistors. The impurity concentrations of the layers 10' and 10 are higher than that in the regions 13' and 12'. The position of the peak of the impurity concentration is set within approximately 0.8mum from the surface of the substrate. Since the two-dimensional distribution of depletion layers in the regions 12' and 13' can be suppressed, the decrease in threshold voltage can be suppressed. Since the electric field of a drain is weakened by the layers 10' and 10, punch-through between a source and the drain is suppressed, and breakdown strength between the source and the drain is improved.

7. 发明专利

JPH0562496A SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURE OF THE SAME 失效
公开(公告)号：JPH0562496A
公开(公告)日：1993-03-12
申请号：JP24685291
申请日：1991-08-30
申请人： HITACHI LTD
发明人： HONJO SHIGERU , YOSHIZAKI KAZUO
IPC分类号： G11C29/00 , G11C29/04 , H01L21/66 , H01L21/82
摘要： PURPOSE:To suppress the increase of a layout area as much as possible, as for a defect bit relief. CONSTITUTION:Conductive lines PDLO-PDLi for supplying a power source to plural bit lines are shared by the pertinent plural bit lines. The pertinent conductive lines are cut so that the power supply to the bit lines corresponding to the conductive lines can be stopped. It is not necessary to form switches or the like at each bit line BLO-BLi, and leak currents can be reduced without increasing the area of the layout area, by using the conductive lines PDLO-PDLi shared by the plural bit lines.

8. 发明专利

JPH04206964A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04206964A
公开(公告)日：1992-07-28
申请号：JP33950390
申请日：1990-11-30
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI HOKKAI SEMICONDUCTOR
发明人： YAMAZAKI YASUSHI , MORIWAKI NOBUYUKI , HISAKAWA HIROYUKI , HONJO SHIGERU , OGURA KAZUTOMO , MOMII MASATO , NAKAMURA HIDEAKI
IPC分类号： H01L21/822 , H01L21/8238 , H01L21/8244 , H01L27/04 , H01L27/092 , H01L27/11
摘要： PURPOSE:To prevent noise generated by the switching of a post stage circuit from being transmitted to an initial stage circuit and reduce the influence of the power source noise by separating the well of the initial stage circuit from the well of the post stage circuit when the initial stage circuit and the post stage circuit connected to it are provided. CONSTITUTION:A post stage circuit 20 is the serial circuit of inverters formed by MOSFETs Q5 and Q6, Q7 and Q8, Q9 and Q10 and an address signal taken by an initial stage circuit 10 is subjected to a prescribed delay through the inverters. The circuit has P-well CMOS structure which produces a P-channel MOSFET on an N-type substrate and an N-channel MOSFET in a P-well, and a well W1 which forms the initial stage circuit 10 and a well W2 which forms the post stage circuit 20 are separated. Thus, the fluctuation of a power source VSS caused by the switching of the post stage circuit 20 is prevented from being transmitted to the well W1 of the initial stage circuit 10, the fluctuation of logical threshold caused by the power source VSS is suppressed and the input level margin of the initial stage circuit 10 is improved.

9. 发明专利

JPH02172273A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02172273A
公开(公告)日：1990-07-03
申请号：JP32582588
申请日：1988-12-26
申请人： HITACHI LTD
发明人： MEGURO SATOSHI , UCHIBORI KIYOBUMI , SUZUKI NORIO , MOTOYOSHI MAKOTO , KOIKE ATSUYOSHI , YAMANAKA TOSHIAKI , SAKAI YOSHIO , HONJO SHIGERU , MINATO OSAMU , KAGA TORU , HASHIMOTO NAOTAKA , HASHIMOTO KOJI
IPC分类号： H01L27/01 , H01L21/8244 , H01L27/00 , H01L27/11
摘要： PURPOSE:To increase the freedom of memory cell layout by arranging the gate electrode of an MISFET for load on the upper part of the gate electrode of an MISFET for driving, and arranging source drain and channel regions of the MISFET for load on the upper part of the gate electrode of the MISFET for load. CONSTITUTION:In the memory cell of a CMOS type SRAM MISFET's Qp1, Qp2 for load are arranged on the upper part of MISFET's Qd1, QD2 for driving. The MOSFET's for load have gate electrodes 34 different from gate electrodes 27 of the MISFET's for driving. As a result, source.drain and channel regions 37A-37C of the MISFET's Qp1, Qp2 for load can be laid out almost without restrictions to the gate electrodes 27 of the MISFET's Qd1, Qd2 for driving. Thereby the freedom of memory cell layout can be increased.

10. 发明专利

JPH01124251A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH01124251A
公开(公告)日：1989-05-17
申请号：JP28237287
申请日：1987-11-09
申请人： HITACHI LTD
发明人： ISHIBASHI KOICHIRO , MINATO OSAMU , HONJO SHIGERU , SASAKI TOSHIO , MASUHARA TOSHIAKI
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/02 , H01L27/06 , H01L27/088 , H03F1/42 , H03F1/52
摘要： PURPOSE:To enhance electrostatic breakdown strength sufficiently even when a current- limiting resistor connected to an input terminal of a protective element is not contained or when only a resistor with an extremely small value can be connected by a method wherein the current-limiting resistor is used between a first constant-voltage clamping element and a second constant-voltage clamping element. CONSTITUTION:When static electricity is impressed on a terminal 1, an electric current ID at an input node D flows to a grounding terminal 103 mainly through a protective resistor 2, a first constant-voltage clamping element 4 and a parasitic resistor 7. In this case, although a potential at a node E is clamped with reference to a node G, a potential at the node G is increased due to the resistor 7 and an electric current; as a result, it is not possible to suppress the potential to a sufficiently small voltage capable of protecting a gate insulating film. However, when a diode 102 is connected as a second constant-voltage clamping element, it is connected to a power-supply wiring part which is different from the MOS FET 4; as a result, it is possible to clamp a potential at a node F to a sufficiently small potential. In this case, a current- limiting resistor 101 functions so as to limit an electric current flowing through the diode 102 and a resistor 9 and to suppress an increase of the potential at the node F.

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