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1. 发明专利

JPH0722463A TAPE CARRIER PACKAGE TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0722463A
公开(公告)日：1995-01-24
申请号：JP16092093
申请日：1993-06-30
申请人： HITACHI LTD
发明人： KANEMITSU NOBUYA , TAKAYAMA KAZUTOSHI , SASAKI MITSUAKI , YAMADA MUNEHIRO , KOIZUMI RYOICHI
IPC分类号： H01L21/60
摘要： PURPOSE:To enable stable recognition of positions in both the X and Y directions in inner lead bonding by forming an inner lead for inner lead X and Y recognition and reinforcement at each of the four corners of the external electrode forming region on the semiconductor chip in a device hole. CONSTITUTION:An inner lead 4 for inner lead X and Y recognition and reinforcement is formed at each of the four corners of the external electrode forming region on the semiconductor chip 3 in a device hole 2. For example, T-shaped inner leads 4, 40mum in width and 400mum in length in both the X- and Y- directions, composed of copper, are formed at the four corners of the external electrode forming region on the semiconductor chip 3 in a carrier tape device hole 2. This reinforces the other inner leads in both the X- and Y-directions, which reduces unevenness in the direction of tape thickness and stabilizes the recognition of fine-pitch inner leads 1.

2. 发明专利

JPH03253048A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH03253048A
公开(公告)日：1991-11-12
申请号：JP5066490
申请日：1990-03-01
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , HITACHI MICROCUMPUTER ENG
发明人： SASAKI MITSUAKI , YAMADA MUNEHIRO , ICHIHARA SEIICHI
IPC分类号： H01L21/60
摘要： PURPOSE:To uniformize the film thickness of a plated film on lead wirings and to contrive an increase in the reliability of a device by a method wherein a dummy lead, which is arranged along the vicinities of the inner lead parts of the lead wirings, is formed simultaneously with the lead wirings. CONSTITUTION:In case a plating treatment is performed on lead wirings 2 formed by patterning on the surface of an insulating film 1 using an electrolytic plating method, a dummy lead 5, which is previously arranged along the vicinities of inner lead parts 2a of the wirings 2, is formed simultaneously with the wirings 2. If there is the dummy lead 5, part of charge, which is concentrated on the points of the lead parts 2a, is attracted to the lead 5 and the concentration of the charge on the points of the lead parts 2 is relaxed. As a result, the film thickness of a plated film on the wirings 2 is uniformized and an improper short-circuit between the lead wirings, which is caused by a local increase in the film thickness of the plated film, can be prevented.

3. 发明专利

JPS62249435A SENICONDUCTOR DEVICE 失效
公开(公告)号：JPS62249435A
公开(公告)日：1987-10-30
申请号：JP9204286
申请日：1986-04-23
申请人： HITACHI LTD
发明人： MATSUKAWA KEIZO , MIYAMOTO KEIJI , YAMADA MUNEHIRO
IPC分类号： H01L23/50 , H01L21/60 , H01L23/48
摘要： PURPOSE:To suppress creation of whiskers and avoid shor circuit between leads each other or between a lead and a bump by a method wherein the thickness of a surface treatment metal layer on the lead is made to be thin at the part which is jointed with the electrode and the thickness of the metal layer is made to be thin at the part other than jointing part. CONSTITUTION:The thickness of an Sn plating layer 5 on a lead 3 is made to be thinner at the part which is bonded to a bump electrode 2. Even if the thickness of the layer 5 is reduced like this, as bonding is carried out between Au bump metal of the bump electrode 2 and Sn of the Sn plating layer 5, creation of whiskers can be suppressed. Therefore, the short circuit between leads 3 of a lead frame each other caused by the growth of whiskers can be avoided. Moreover, by reducing the thickness, the creation of excessive Au-Sn alloy is suppressed and short circuit between the lead 3 and the bump 2 caused by the excessive alloy can be avoided. Further, by increasing the thickness of an Sn plating layer 6, stress on the surface of the plating layer 6 can be relieved and the creation of whiskers is suppressed and short circuit between the leads each other can be avoided in the same way.

4. 发明专利

JP2001044361A LAMINATED MULTI-CHIP SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001044361A
公开(公告)日：2001-02-16
申请号：JP2000204078
申请日：2000-07-05
申请人： HITACHI LTD
发明人： SAKAGUCHI MASARU , ISHIDA TOSHIHARU , ASHIZAWA KOJI , TANAKA HIROYUKI , MIYANO ICHIRO , YAMAZAKI KAZUO , YAMADA MUNEHIRO
IPC分类号： H01L25/18 , H01L25/10 , H01L25/11
摘要： PROBLEM TO BE SOLVED: To provide a mass storage multi-chip semiconductor device for ensuring high reliability of a connection part. SOLUTION: In a stack multichip semiconductor device, plural tape carriages where semiconductor chips are connected electrically to film carrier tapes having wiring patterns on at least one face are laminated/connected via connector frames 2a and 2b. A lead 15a of the film the carriage package is extended, so that it protrudes to a side outside of the end faces of connector frame terminals 26a and 27b and a solder fillet is formed between the tape carrier packages via the lead 15a extended, so that it protrudes and connect them.

5. 发明专利

JPH07245324A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07245324A
公开(公告)日：1995-09-19
申请号：JP3556594
申请日：1994-03-07
申请人： HITACHI LTD
发明人： MIYANO ICHIRO , SERIZAWA KOJI , SAKAGUCHI MASARU , ISHIDA TOSHIHARU , YAMADA MUNEHIRO
IPC分类号： H01L21/60 , H01L23/29 , H01L23/50 , H01L25/065 , H01L25/07 , H01L25/10 , H01L25/11 , H01L25/18
摘要： PURPOSE:To directly lead out a heat sink to the outside of a package, the whole body of which is formed by molding a resin, from an IC chip so as to highly effectively radiate the heat from the IC chip to the outside by exposing the end sections of outer leads and the heat sink from the molded resin body. CONSTITUTION:After electrically connecting an IC chip 2 with a carrier tape 1, a heat sink 3 made of a material having high heat conductivity is mounted on the rear surface of the chip 2. Then the chip 2 is sealed by molding an epoxy resin in a prescribed shape around the chip 2. At the time of molding, the end section of the heat sink 3 is exposed from the molded resin body. After sealing the chip 2 with the resin, the heat sink is molded so that it can be a heat pipe front heat radiating fins or the chip 2 to a mounting substrate at the time of forming outer leads. Then the heat sink 3 is soldered to a prescribed part of a heat radiating pattern 7 provided on the substrate. Therefore, the heat generated from the chip 2 can be radiated with high efficiency.

6. 发明专利

JPH06260530A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH06260530A
公开(公告)日：1994-09-16
申请号：JP4774393
申请日：1993-03-09
申请人： HITACHI LTD
发明人： TANAKA HIDEKI , YAMADA MUNEHIRO
IPC分类号： H01L21/60
摘要： PURPOSE:To improve the mounting density of a semiconductor chip compared with a surface-mount package and a tape carrier package by directly connecting the semiconductor to a wiring on a mounting substrate. CONSTITUTION:A large number of wirings 2, in which, for instance, a Cu foil stuck to this mounting board 1 is patterned by etching, are provided on one face of the mounting board 1 consisting of epoxy resin impregnated with glass fibers or the like. Further, a rectangular opening holes 3 is provided about in the center of the mounting board 1 and the respective one ends of the wirings 2 are arranged so as to project inside this opening 3. And the one ends of these wirings 2 are extended on the bonding pad of a semiconductor chip 4 arranged inside this opening 3 and electrically connected to the bonding pad through a bump electrode. Thereby, a large number of semiconductor chips 4 can be mounted.

7. 发明专利

JPH01233742A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01233742A
公开(公告)日：1989-09-19
申请号：JP6162588
申请日：1988-03-14
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： ICHIHARA SEIICHI , YAMADA MUNEHIRO , MATSUKAWA KEIZO
IPC分类号： H01L21/60
摘要： PURPOSE:To form a bump electrode whose height is even by a method wherein a metal paste for bump electrode formation is filled into an opening of a mask on a substrate, the mask is removed and, after that, a heat treatment is executed. CONSTITUTION:An opening 5 is formed on a wiring part 3 in a passivating film 4 as an uppermost layer; the wiring part 3 is exposed. A substratum metal film 6 is formed on the whole surface on a substrate 1. A resist film 7 is coated or pasted on the passivating film 4; an opening 8 is formed only on the metal film 6 in the resist film 7. A metal paste 9 for bump electrode formation use is thrust and filled into the opening 8. A solvent in the paste 9 is volatilized; the resist film 7 is removed. After that, a baking operation is executed; a bump electrode 9A is formed. By this setup, the bump electrode 9A whose height is even can be formed.

8. 发明专利

JPS6427246A SEMICONDUCTOR UNIT AND MANUFACTURE 失效
公开(公告)号：JPS6427246A
公开(公告)日：1989-01-30
申请号：JP18445187
申请日：1987-07-22
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YAMADA MUNEHIRO , ICHIHARA SEIICHI , WAKASHIMA YOSHIAKI
IPC分类号： H01L21/60
摘要： PURPOSE:To reduce load on bonding for improved reliability of junction by performing junction of valve electrode and lead on semiconductor pellet by forming eutectic (or alloy). CONSTITUTION:A small bonding load is applied to and heating is performed at a relatively low temperature while a metal 9C of lead 9 is in contact with the second metal layer 7B consisting of tin layer of bump electrode 7. As a result, the tin diffuses the first metal layer 7A consisting of the bump electrode metal layer and the lead metal layer 9C to form an eutectic of Au and Sn 10. the bonding load at this time is small as compared with the strength of a passivation film 5. It will prevent crack to be generated on the passivation film 5. Also, since the junction between the lead 9 and a bump electrode 7 is formed by eutectic (or alloy), the reliability of junction is great.

9. 发明专利

JPS6379332A FILM CARRIER 失效
公开(公告)号：JPS6379332A
公开(公告)日：1988-04-09
申请号：JP22359386
申请日：1986-09-24
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： ICHIHARA SEIICHI , MIYAMOTO KEIJI , MATSUKAWA KEIZO , YAMADA MUNEHIRO
IPC分类号： H01L21/60 , H01L21/66
摘要： PURPOSE:To obtain a film carrier which is available for testing and which also has antistatic effect, by laminating or spreading an antistatic layer on the peripheral part separated from a pad for testing and the peripheral part of a sprocket. CONSTITUTION:An antistatic layer 6 constituted of conductor foils or carbon tapes in the case of forming a lead is laminated or spread on the peripheral part separated from a pad 5 for testing and the peripheral part of sprocket holes 2. As an antistatic area is formed on the peripheral part of a sprocket holes 2, electrification is reduced, even if a tape is carried by the sprocket holes 2, or a reel and a tape 1 contact with each other. Thereby, a film carrier which is available for test and also has antistatic effect can be obtained.

10. 发明专利

JP2003194690A IMPACT TEST METHOD, IMPACT TESTING DEVICE AND RELIABILITY EVALUATION METHOD OF SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003194690A
公开(公告)日：2003-07-09
申请号：JP2001395631
申请日：2001-12-27
申请人： HITACHI LTD
发明人： YAGUCHI AKIHIRO , YAMADA MUNEHIRO , FUKUSHIMA SHINJI
IPC分类号： G01N3/303 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To evaluate highly accurately the reliability of a test object by suppressing generation of disturbance of a substrate strain waveform caused by re-collision of a dropping object with a printed wiring board or contact between the dropping object and the printed wiring board, in an impact test for evaluating the reliability of a solder connection part of a semiconductor device mounted with solder onto the printed wiring board, by allowing the dropping object to collide with the printed wiring board. SOLUTION: A structure for preventing re-collision of a dropping probe colliding with the test object is provided. A long cylindrical probe is used as the dropping object, and a mechanism for grasping the probe after collision with the printed wiring board is provided. COPYRIGHT: (C)2003,JPO

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