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1. 发明专利

JP2010056212A Semiconductor integrated circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路装置及其制造方法
公开(公告)号：JP2010056212A
公开(公告)日：2010-03-11
申请号：JP2008218086
申请日：2008-08-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： WATANABE TOKUO
IPC分类号： H01L21/8234 , H01L21/329 , H01L21/76 , H01L21/762 , H01L27/08 , H01L27/088 , H01L29/786 , H01L29/861
CPC分类号： H01L29/7824 , H01L21/76264 , H01L29/0692
摘要： PROBLEM TO BE SOLVED: To make it possible to raise a dielectric voltage between a high voltage metal electrode and a low voltage electrode. SOLUTION: In a semiconductor integrated circuit device including: a high voltage semiconductor 210 including a support substrate 5, an insulating film 6 laminated on the support substrate, and a first semiconductor layer 8 laminated on the insulating film; and a control circuit, the high voltage semiconductor 210 comprises an interior dielectric separation region 701, where a closed loop shape insulating film is so formed as to surround the first semiconductor layer; an exterior dielectric separation layer 702, where a closed loop shape insulating film is formed in the perimeter of the interior dielectric separation region; a second semiconductor layer 81 formed between the interior dielectric separation region and the exterior dielectric separation region on the surface of the insulating film; a field oxide film 50 laminated on the interior dielectric separation region, the exterior dielectric separation region, and the surface of the second semiconductor region; and a metal electrode 3 formed on the surface of the field oxide film while being connected to the first semiconductor layer. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：使得可以提高高压金属电极和低电压电极之间的介电电压。解决方案：一种半导体集成电路器件，包括：包括支撑衬底5的高电压半导体210，层叠在支撑衬底上的绝缘膜6和层叠在绝缘膜上的第一半导体层8; 和控制电路，高电压半导体210包括内部电介质分离区域701，其中围绕第一半导体层形成闭环形绝缘膜; 外部介电分离层702，其中在内部介电分离区域的周边形成闭环形绝缘膜; 形成在绝缘膜表面上的内部介电分离区域和外部电介质分离区域之间的第二半导体层81; 层叠在内部电介质分离区域，外部电介质分离区域和第二半导体区域的表面上的场氧化物膜50; 以及形成在场氧化膜的表面上同时连接到第一半导体层的金属电极3。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2007080288A Interface device 有权
标题翻译：接口设备
公开(公告)号：JP2007080288A
公开(公告)日：2007-03-29
申请号：JP2006307900
申请日：2006-11-14
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KIKUCHI MUTSUMI , MURABAYASHI FUMIO , SASE TAKASHI , WATANABE TOKUO , AJIRO YUUJI
IPC分类号： G06F3/00
CPC分类号： H01L2924/14
摘要： PROBLEM TO BE SOLVED: To provide an interface device using a dielectrically isolated substrate that sufficiently suppresses malfunction and characteristic degradation due to noise.
SOLUTION: In the interface device, in which an SOI substrate 414 is divided, by a buried insulation film 412 and a region insulation part 410, into a semiconductor support substrate region 411, a controller side region 407, and a network side region 408, and capacitive isolator circuits 405 and 406 are partly formed in the network side region 408, the semiconductor support substrate region 411 and the network side region 408 are connected to a network power supply to continuously maintain the same potential.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种使用能够充分抑制因噪声引起的故障和特性劣化的介电隔离基板的接口装置。解决方案：在其中SOI衬底414被掩埋绝缘膜412和区域绝缘部分410分成半导体支撑衬底区域411，控制器侧区域407和网络侧的接口器件中区域408和电容隔离电路405和406部分地形成在网络侧区域408中，半导体支撑衬底区域411和网络侧区域408连接到网络电源以连续地保持相同的电位。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2006093382A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006093382A
公开(公告)日：2006-04-06
申请号：JP2004276565
申请日：2004-09-24
申请人： Denso Corp , Hitachi Ltd , 株式会社デンソー , 株式会社日立製作所
发明人： OYANAGI TAKASUMI , WATANABE TOKUO , SAKAKIBARA TOSHIO , YAMAMOTO TAKESHI , NAKAMURA HIROKI , MALHAN RAJESH KUMAR
IPC分类号： H01L27/095 , H01L21/822 , H01L21/8232 , H01L27/04 , H01L27/06 , H01L29/47 , H01L29/80 , H01L29/861 , H01L29/872
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/8083
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device which incorporates a temperature measuring diode that can be operated at a high temperature and which can be used under a high temperature environment.
SOLUTION: When a structure where grooves 110 and 111 are used for control regions 12 and 14 is adopted as an electrostatic induction transistor, a normally-off device can be obtained in accordance with a distance between control layers. Normally-off device is used as inter-element separation, and a hetero-junction diode 114 (or pn junction diode) is constituted of silicon carbide and polycrystalline silicon. Inter-element separation is realized by grounding a deep p-type third layer 30. The temperature measuring diode can be formed between an n-type fourth layer on an inner side and the other face of a substrate.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种碳化硅半导体器件，其包含可在高温下操作并可在高温环境下使用的温度测量二极管。解决方案：当将控制区域12和14用作沟槽110和111的结构用作静电感应晶体管时，可以根据控制层之间的距离获得常关器件。正常关断器件用作元件间隔离，异质结二极管114（或pn结二极管）由碳化硅和多晶硅构成。通过使深p型第三层30接地来实现元件间分离。温度测量二极管可以形成在内侧的n型第四层和衬底的另一面之间。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2002270825A METHOD OF MANUFACTURING FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002270825A
公开(公告)日：2002-09-20
申请号：JP2001064318
申请日：2001-03-08
申请人： HITACHI LTD
发明人： OYANAGI TAKASUMI , WATANABE TOKUO
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/08 , H01L29/10 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To miniaturize an MOS field effect transistor, without deteriorating the breakdown voltage of it. SOLUTION: The electric field relieving layer of gate overlapping structure is arranged by bringing it into contact with a drain region, a distance between the electric field relieving layer and a high concentration layer is spread and an electric field is relieved. Since an equal potential line is bent by a gate insulating film, the electric field is relieved much more. A punch-through stopper layer of a gate overlap structure is arranged by bringing it into contact with the source region, the spreading of a depletion layer to the source region is suppressed, and gate length made fine.

5. 发明专利

JP2001235382A ELECTROSTATIC CAPACITY TYPE PRESSURE SENSOR 失效
公开(公告)号：JP2001235382A
公开(公告)日：2001-08-31
申请号：JP2000052187
申请日：2000-02-23
申请人： HITACHI LTD , HITACHI CAR ENG CO LTD
发明人： ONOSE YASUO , WATANABE TOKUO , KURIO SEIJI , SATO SHINYA , HORIE JUNICHI , SHIMADA SATOSHI
IPC分类号： G01L9/12 , G01L1/14 , G01L9/00 , H01L29/84
摘要： PROBLEM TO BE SOLVED: To improve the detecting precision of an electrostatic capacity type pressure sensor by reducing a parasitic capacitance. SOLUTION: In this electrostatic capacity type pressure sensor constituted by having a plurality of pressure sensor units disposed on a substrate 1 and connected in parallel, each of which units is provided with an electrode 3, a hollow area 8, and a diaphragm including a conductive film 6 opposite to the electrode through the hollow area 8, a diaphragm fixing portions 7 are provided in the hollow area so that one diaphragm is partitioned into a plurality of sensor units, thereby making an invalid area smaller to reduce a parasitic area.

6. 发明专利

JP2001168327A SEMICONDUCTOR DEVICE AND POWER SWITCHING DRIVE SYSTEM PROVIDED WITH THE SAME 失效
公开(公告)号：JP2001168327A
公开(公告)日：2001-06-22
申请号：JP34978599
申请日：1999-12-09
申请人： HITACHI LTD
发明人： SAKAMOTO MITSUZO , INOUE HIRONORI , MIYAUCHI AKIHIRO , SHIRAISHI MASAKI , MORI MUTSUHIRO , WATANABE TOKUO , OYANAGI TAKASUMI
IPC分类号： H01L21/336 , H01L29/04 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/12 , H01L29/423 , H01L29/732 , H01L29/739 , H01L29/772 , H01L29/78 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To enable a semiconductor device to be improved in withstand voltage and lessened in power loss. SOLUTION: A semiconductor device is equipped with a first terminal 101 (source terminal) and a second terminal 102 (drain terminal), the substrate main surface of the semiconductor chip of the semiconductor device is a (110) crystal plane, the n-type region 2a and p-type region 4 of the semiconductor chip are so processed as to enable a 111} crystal plane vertical to the (110) crystal plane to serve as a main contact surface taking advantage of an anisotropic etching process, n-type regions 2 and p-type regions 4 alternately arranged adjacent to each other extending slenderly in the direction of a [110] axis are made to form a voltage holding region, the first terminal 101 is connected to the p-type region 4 with a wiring, and the second terminal 102 is connected to the n-type region 2. The p-type region A is formed so as to cover the base corner of a gate polycrystalline silicon layer 8.

7. 发明专利

JPH11258089A SEMICONDUCTOR PRESSURE SENSOR 失效
公开(公告)号：JPH11258089A
公开(公告)日：1999-09-24
申请号：JP6250398
申请日：1998-03-13
申请人： HITACHI LTD , HITACHI CAR ENG CO LTD
发明人： SHIMADA SATOSHI , SAITO AKIHIKO , MATSUMOTO MASAHIRO , WATANABE TOKUO , ICHIKAWA NORIO , MIYAZAKI ATSUSHI , HORIE JUNICHI , HANZAWA KEIJI
IPC分类号： G01L9/12 , H01L29/84
摘要： PROBLEM TO BE SOLVED: To provide a highly stable pressure sensor uninfluenced by a measuring fluid and atmospheric pressure by providing a recessed cap for almost vacuously sealing fixed/movable both electrodes, and arranging a shielding electrode for protecting both electrodes from an external electric noise in the cap. SOLUTION: A fixed electrode 126 is protected from moisture and contamination from outside since it is arranged in a space formed by being airtightly sealed by a polysilicon cap 128 and a sensor substrate 1 to prevent electric potential influence from this. The space is vacuously sealed, so that pressure applied to a diaphragm 121 is measured as an absolute pressure reference. A void 125 forms pressure detecting capacitance between a movable electrode 123 and a fixed electrode 126 formed on the sensor substrate 1. The substrate 1 and the diaphragm 121 are held in prescribed electric potential to prevent electric potential of a measuring object fluid from influencing the movable electrode 123. The polysilicon cap 128 formed on this to prevent influence of an atmospheric pressure change, gas a function of a shielding electrode to prevent the fixed electrode 126 from being contaminated from outside.

8. 发明专利

JPH09237904A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JPH09237904A
公开(公告)日：1997-09-09
申请号：JP4243196
申请日：1996-02-29
申请人： HITACHI LTD
发明人： ISHIKAWA KATSUMI , SAITO KATSUAKI , KATO SHUJI , WATANABE TOKUO , MONMA NAOHIRO
IPC分类号： H01L29/74 , H01L21/265 , H01L21/322 , H01L29/06 , H01L29/32 , H01L29/861 , H01L31/111
摘要： PROBLEM TO BE SOLVED: To improve the relation between the reverse recovered charge and ON-voltage by forming so as to increase the lattice defect density from one main surface to the other. SOLUTION: The impurity concn. distribution of a diode is as shown by the structure of a high concn. n-type layer 21, low concn. n-type layer 22 and p-type layer 2. A lattice defect region 11 due to the proton or He ion irradiation is provided in the substrate depth direction from an anode electrode 42 to a cathode electrode 41 and formed so as to increase the lattice defect density from the anode to the cathode. Owing to the high concn. n-type layer 21, the electron density in the conduction state before introduction of the lattice defect is higher at the cathode 41 and hence the electron density in the conduction state after introduction of the lattice defect is flat from the anode 42 to the cathode 41. This suppresses the rise of the ON-voltage and improves the trade off of the reverse recovered charge.

9. 发明专利

JPH07335773A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH07335773A
公开(公告)日：1995-12-22
申请号：JP12892394
申请日：1994-06-10
申请人： HITACHI LTD
发明人： SATO KAZUE , WATANABE TOKUO , KIKUSHIMA KENICHI , OWADA NOBUO , IIDA MASAYA
IPC分类号： H01L21/285 , H01L21/8249 , H01L27/06
摘要： PURPOSE:To prevent the formation of a silicide layer on a main surface of an emitter electrode by covering the main surface of the emitter electrode with a first insulating film in forming the silicide layer on main surfaces of a second semiconductor region and a third semiconductor region. CONSTITUTION:An n-channel MISFET Qn is formed on a main surface of a p-type well region 6 with its periphery limited by a field insulating film 4. A gate insulating film 10 is formed on the main surface of the p-type well region 6. A gate electrode 11 is formed on a main surface of the gate insulating film 10 and is formed by polycrystalline silicon and a silicide layer 24 formed on a main surface of a polycrystalline silicon film. An intrinsic base region is formed by a p-type semiconductor region 14. An emitter electrode 16 is provided to lower the resistance value, and is formed by a polycrystalline silicon film doped with n-type impurity. A graft base region is formed by a p-type semiconductor region 22 formed on a main surface of an n-type epitaxial layer 1B. The silicide layer 24 is formed by self-alignment to a side wall spacer 20 covering lateral sides of the emitter electrode 16.

10. 发明专利

JPH061781B2 失效
公开(公告)号：JPH061781B2
公开(公告)日：1994-01-05
申请号：JP8625785
申请日：1985-04-24
申请人： HITACHI LTD
发明人： HONMA HIDEO , MISAWA YUTAKA , MONMA NAOHIRO , NAGANO TAKAHIRO , IKEDA TAKAHIDE , WATANABE TOKUO , YAMADA KOICHIRO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72

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