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1. 发明专利

DE2616648A1 CIRCUIT FOR KEYBOARD FEEDING INFORMATION - by use of input annaand locking keys uses timing pulses on multiplex principle operated by integrated semiconductor logic 未知
公开(公告)号：DE2616648A1
公开(公告)日：1976-11-11
申请号：DE2616648
申请日：1976-04-15
申请人： HITACHI LTD
发明人： NOMIYA KOSEI , TORII SHUICHI , HARA HIDEO
IPC分类号： G06F3/02 , H03M11/20 , H01H13/70 , H04L17/04
摘要： Keyboard input circuit for feeding in information using input keys and locking keys. Control is via timing pulses using multiplex principles. A digital section of the system is made from an integrated semi-conductor circuit with push-button input. This system also contains other digital circuits such as memories, arithmetic operating networks, control networks and generators for the timing pulses. A multi-channel coded signal is produced via the timing pulse. The decoding circuit is connected to the N-ear coding network to convert the output signals into a number of digital pulses. The multi-channel coded signal is fed to a gating circuit, a second gating circuit is connected between the keyboard and the first gating circuit to prevent any faulty digital signals if more than one key is depressed simultaneously.

2. 发明专利

DE3364066D1 A PULSE WIDTH MODULATION CIRCUIT AND AN ANALOG PRODUCT FORMING INTEGRATION CIRCUIT USING SUCH MODULATION CIRCUIT 未知
公开(公告)号：DE3364066D1
公开(公告)日：1986-07-17
申请号：DE3364066
申请日：1983-07-27
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAGI KATSUAKI , KITA YUZO , HAGIWARA YOSHIMUNE , OGAWA KAZUYOSHI , HARA HIDEO
IPC分类号： G01R22/00 , G01R21/127 , G06G7/161 , G06G7/186 , H03K7/06 , H03K7/08 , H03M1/50 , H03M1/82
摘要： A pulse width modulation circuit is capable of cancelling the mean error of pulse width modulation with respect to time due to the offset voltage of a triangular wave signal and to the offset voltage of a comparator, by adding simple circuits (FF3, L1, L2) to an existing pulse width modulation circuit (10, CP3). Such pulse width modulation circuit is used preferably in an integration circuit forming the product of two analog signals.The offset of the triangular wave signal (VA) is cancelled by inverting either the triangular wave signal with respect to the input signal or the input signal with respect to the triangular wave signal, in every predetermined period. To this end, the circuit eliminates the offset of a comparator (CP3) by inverting the output of the comparator and replacing the input terminals of the comparator if the input signal is not inverted, or connecting the input terminal of the comparator as such if the input signal is inverted.

3. 发明专利

JPH0887885A SEMICONDUCTOR MEMORY CIRCUIT 失效
公开(公告)号：JPH0887885A
公开(公告)日：1996-04-02
申请号：JP22021894
申请日：1994-09-14
申请人： HITACHI LTD
发明人： NISHIO YOJI , HIROSE KOSAKU , NOTO TAKAYUKI , HARA HIDEO , KOIKE KATSUNORI
IPC分类号： G11C11/408 , H01L21/82 , H01L27/118
摘要： PURPOSE: To obtain a compiled system memory where word lines and bit lines are arranged at fine pitch by assigning an insignificant bit of address to Y address and a significant bit to X address. CONSTITUTION: A Y address system comprises an address buffer 12 receiving a most insignificant bit address A0, Y decoders 0 and 1, Y switches 0-2, 0-3 receiving an output from the Y decoder 0, and Y switches 1-2, 1-3 receiving an output from the Y decoder 1. An X address system comprises address buffers 13, 14 receiving significant bit addresses A1, A2, an X predecoder 15 receiving outputs therefrom, and X main decoders 00, 01, 10, 11 receiving outputs from the X predecoder. The X main decoder 00 accesses a memory cell in the lowermost row and respective X main decoders correspond to respective rows.

4. 发明专利

JPH0766710A INPUT/OUTPUT BUFFER CIIRCUIT 失效
公开(公告)号：JPH0766710A
公开(公告)日：1995-03-10
申请号：JP21178793
申请日：1993-08-26
申请人： HITACHI LTD
发明人： NISHIO YOJI , IWAMURA MASAHIRO , HOSONO TOMOHISA , HARA HIDEO
IPC分类号： G06F3/00 , G11C11/409 , H01L21/8238 , H01L27/092 , H03K19/003 , H03K19/0175
摘要： PURPOSE:To exclude a leakage current in an I/O buffer circuit for executing I/O operation to/from a device with a power supply voltage level higher than its own power supply voltage. CONSTITUTION:In the case of outputting an 'L' level signal to an I/O terminal 7, an I/O control circuit 11 respectively impresses 'H' level voltage and Vcc1 level voltage to the gate terminal of a PMOS P1 and the gate terminal of NMOS NO2. Since the PMOS P1 is turned off and the NMOS NO2 is turned on as the result of the voltage impression, an I/O terminal 7 goes to an 'L' level. Simultaneously a PMOS P3 is turned on and the gate terminal of the PMOS P1 is raised up to the VCC1 level, so that the PMOS P1 is completely turned off and no leakage current flows. Even when an 'H' level signal is inputted to the I/O terminal 7, the PMOS P1 is completely turned off and a leakage pass from the terminal 7 to power supply Vcc1 through the PMOS P1 is interrupted.

5. 发明专利

JPS62188098A SEMICONDUCTOR READ ONLY MEMORY 失效
公开(公告)号：JPS62188098A
公开(公告)日：1987-08-17
申请号：JP26370186
申请日：1986-11-07
申请人： HITACHI LTD
发明人： HARA HIDEO , KEIDA HARUO
IPC分类号： G11C17/18 , G11C17/00
摘要： PURPOSE:To accelerate access, by dividing a MOSFET connected in series to the output line of a memory matrix into plural groups, and synthesizing an output signal from each group. CONSTITUTION:MOSFETs M01 and M02 in ROM circuits 2 and 3 that a MOSFET connected in series is divided into two, are turned on with a clock pulse phix, and pre-charge capacitors C1 and C2 with a negative power source, the inverse of VDD. Next, when the FETs M01 and M02 are turned off, and FETS M11-M1n, and M21-M2m conduct according to the states of input signals A11-A2m, the electric charge of the capacitors C1 and C2 are discharged. Therefore, the same output O3 as the one made by synthesizing the outputs of output terminals O1 and O2 with a NOR circuit 4, and forming all of the MOSFETs in series, can be obtained and also, a time constant is reduced by division, and the access can be made into the high speed.

6. 发明专利

JPS59117669A Integration circuit 失效
标题翻译：集成电路
公开(公告)号：JPS59117669A
公开(公告)日：1984-07-07
申请号：JP22627982
申请日：1982-12-24
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： TORII SHIYUUICHI , HARA HIDEO , KIDA YUUZOU , TAKAGI KATSUAKI , OGAWA KAZUYOSHI
IPC分类号： G06G7/186 , G06G7/184
CPC分类号： G06G7/184
摘要： PURPOSE:To make the resultant offset voltage of two operational amplifiers coincident with anintegral output having no offset in respect to two periods, by repeating addition and subtraction of this resultant offset voltage each time when the period is changed and allowing it to appear in the integral output. CONSTITUTION:When a timing signal phi is in the high level and MOS FETs Q10-Q17 are turned on, an operational amplifier OP1 is operated as a voltage follower, and MOSFETQ11 is inserted between the non-inverted input of an operational amplifier OP2 and the earth potential, and then, the integrating operation is so performed that the resultant offset voltage is added; and when a timing signal phi' is in the high level and MOSFETs Q20-Q27 are turned on, operations of operational amplifiers OP1 and OP2 are exchanged for said state. Consequently, the integrating operation is so performed that the resultant offset voltage vos is subtracted. The resultant offset is cancelled in respect to two periods T1 and T2, thus attaining an ideal integral output
摘要翻译：目的：为了使两个运算放大器的合成偏移电压与相对于两个周期没有偏移的整体输出相一致，通过每当该周期被改变并且允许它出现在积分中时，重复加法和减去该合成的偏移电压输出。构成：当定时信号phi处于高电平并且MOS FET Q10-Q17导通时，运算放大器OP1作为电压跟随器运行，MOSFETQ11插入在运算放大器OP2的非反相输入端和接地电位，然后进行积分运算，使得产生的偏移电压相加; 并且当定时信号phi'处于高电平并且MOSFET Q20-Q27导通时，运算放大器OP1和OP2的操作被交换为所述状态。因此，进行积分运算，从而减去所产生的偏移电压vos。结果偏移相对于两个周期T1和T2被抵消，从而获得理想的积分输出

7. 发明专利

JPS5922441A Pulse width modulation circuit and digital output type integrating circuit using it 失效
标题翻译：脉冲宽度调制电路和数字输出型集成电路
公开(公告)号：JPS5922441A
公开(公告)日：1984-02-04
申请号：JP13033682
申请日：1982-07-28
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： TAKAGI KATSUAKI , KIDA YUUZOU , HAGIWARA YOSHIMUNE , OGAWA KAZUYOSHI , HARA HIDEO
IPC分类号： G01R22/00 , G01R21/127 , G06G7/161 , G06G7/186 , H03K7/06 , H03K7/08 , H03M1/50 , H03M1/82
CPC分类号： H03M1/82 , H03K7/08
摘要： PURPOSE:To eliminate the offset voltage of a triangle wave generating circuit and of a comparator, by inputting alternately two positive/negative inputs equal in absolute value being the 1st input of a pulse width modulating circuit to the comparator, inverting the output and obtaining a value averaged in time. CONSTITUTION:A switch SW3 switching an AC signal Ev proportional to a voltage of an electric system to be used for measuring the power and its inverting signal -Ev, an EOR logical gate L2 inverting an output Vg of a comparator CP3, and a toggle type flip-flop FF3 inverted by a pulse SDELTA generated once per one period of a triangle wave and outputting a pulse frequency-dividing the SDELTA into a half, are provided additionally between a triangle wave generating circuit 10 and a pulse generating circuit 20. An output ST of the FF3 is a signal switching the switch SW3 and the gate L2 at a prescribed period. The effect of the offset voltage is offset by observing one period of the switching signal ST, i.e., two periods' share of the triangle wave.
摘要翻译：目的：为了消除三角波产生电路和比较器的偏移电压，通过输入两个等于绝对值的正/负输入作为脉冲宽度调制电路的第一输入到比较器，反相输出并获得时间平均值。构成：开关SW3切换与要用于测量功率的电气系统的电压及其反相信号-Ev成比例的交流信号Ev，反相比较器CP3的输出Vg的EOR逻辑门L2和触发类型在三角波产生电路10和脉冲发生电路20之间另外提供由三角波的每个周期一次生成的脉冲SDELTA反相并将SDELTA分频为一半的脉冲输出的触发器FF3。输出 FF3的ST是在规定的周期切换开关SW3和栅极L2的信号。通过观察切换信号ST的一个周期，即三角波的两个周期的共享来抵消偏移电压的影响。

8. 发明专利

JPS5648695A SOUND GENERATION CIRCUIT 失效
公开(公告)号：JPS5648695A
公开(公告)日：1981-05-01
申请号：JP12411079
申请日：1979-09-28
申请人： HITACHI LTD
发明人： TORII SHIYUUICHI , HARA HIDEO , NISHIHARA TATSUYA
IPC分类号： H04R3/00

9. 发明专利

JPS5648692A SOUND GENERATION CIRCUIT 失效
公开(公告)号：JPS5648692A
公开(公告)日：1981-05-01
申请号：JP12410279
申请日：1979-09-28
申请人： HITACHI LTD
发明人： TORII SHIYUUICHI , HARA HIDEO , NISHIHARA TATSUYA
IPC分类号： H04R3/00

10. 发明专利

JPS5570987A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5570987A
公开(公告)日：1980-05-28
申请号：JP14420678
申请日：1978-11-24
申请人： HITACHI LTD
发明人： HARA HIDEO
IPC分类号： G11C11/41 , G11C5/14
摘要： PURPOSE:To reduce power consumption by decreasing the ineffective current in the logic control circuit at chip non-selection, by performing the power supply to the logic control circuit via the power switch controlled with the chip selection signal. CONSTITUTION:The unit 1 constituted with the complementary type MIS circuit provides the static type RAM2 and the logic control circuit 3, and the power supply voltage -VDD is directly fed to RAM2 and it is fed to the circuit 3 via the power switch Q. Further, the switch Q is controlled with the chip selection signal CE via the inverters IN1 and IN2. On the other hand, the word line selection circuit of RAM2 is controlled with the signal CE via the inverter IN2. Thus, the word line of RAM2 is compulsively made to non-selection state at chip non-selection. Further, the threshold voltage between IN2 and IN3 has a difference to make non-selection state the word line of RAM2 and then to turn off Q.

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