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1. 发明专利

JPH0562925A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0562925A
公开(公告)日：1993-03-12
申请号：JP21911291
申请日：1991-08-30
申请人： HITACHI LTD
发明人： TAKAKURA TOSHIHIKO , TAKAHASHI TAKESHI , TANEOKA TADAYUKI , AKIMORI HIROKO , NISHIZAWA HIROTAKA
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/331 , H01L23/52 , H01L29/73
摘要： PURPOSE:To reduce the leak current of a shallow PN junction formed on the semiconductor substrate located on the lower part of a polycrystalline silicon electrode, and to accomplish an excellent ohmic connection between the above- mentioned polycrystalline silicon electrode and the Al metal wiring which will be connected to the electrode. CONSTITUTION:A conductive layer 16, consisting of AlSix (aluminum silicide) or Al-Si alloy, and a barrier metal layer 15, consisting of TiN or TiW, are provided between an emitter lead-out electrode 9, consisting of polycrystalline silicon which is connected to the emitter region 8 of a bipolar transistor, and an Al metal wiring 12a to be connected to the above-mentioned lead-out electrode 9.

2. 发明专利

JPH02250315A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02250315A
公开(公告)日：1990-10-08
申请号：JP7061789
申请日：1989-03-24
申请人： HITACHI LTD
发明人： TANEOKA TADAYUKI , TAKAKURA TOSHIHIKO , TAKAHASHI TAKESHI , SHIBATA JUNICHI
IPC分类号： H01L27/04 , H01L21/266 , H01L21/822
摘要： PURPOSE:To form a plurality of impurity layers in an identical process by a method wherein resist patterns are formed in individual impurity-introduction regions in such a way that ratios of exposed areas are different from each other. CONSTITUTION:When impurity layers are formed individually in a plurality of impurity-introduction regions RL, RM, RH on a semiconductor substrate 1, resist patterns 8 are formed in the individual impurity-introduction regions RL, RM, RH in such a way that ratios of exposed areas are different from each other. Accordingly, impurities of amounts corresponding to the ratios of the exposed areas are introduced into the individual impurity-introduction regions RL, RM, RH; a plurality of impurity layers whose introduction concentrations of the impurities are different can be formed in an identical process. Thereby, since the amounts of the impurities introduced into the individual impurity- introduction regions RL, RM, RH can be controlled, it is possible to form the plurality of impurity layers whose impurity amounts are different by one impurity-introduction operation.

3. 发明专利

JPS6379343A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6379343A
公开(公告)日：1988-04-09
申请号：JP22354286
申请日：1986-09-24
申请人： HITACHI LTD
发明人： WATANABE KUNIHIKO , TANEOKA TADAYUKI
IPC分类号： H01L21/76
摘要： PURPOSE:To increase the area of a field oxide film and to increase the area of an effective interconnection region, by providing an oxide film on the surface of a semiconductor film in order to bury grooves and a field oxide film, which is to become the interconnection region, in a self-aligning mode. CONSTITUTION:After a photoresist 10 is removed, a silicon epitaxial layer 3 undergoes thermal oxidation with an Si3N4 film 5 as a mask. Thus a field oxide film 11 comprising an SiO2 film is formed on the surface of the silicon epitaxial layer 3 at a part, which is not covered with the Si3N4 film 5. An SiO2 film 12 is formed on the surface of polycrystalline silicon films 9, which are buried in U grooves 7 in a self-aligning mode with respect to the field oxide film 11 and in continuation to the field oxide film 11. The field oxide film becomes an interconnection region, which is formed thereon. The U grooves 7 are competely isolated by the SiO2 film 12.

4. 发明专利

JPS63143865A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63143865A
公开(公告)日：1988-06-16
申请号：JP29041186
申请日：1986-12-08
申请人： HITACHI LTD
发明人： WATANABE KUNIHIKO , TANEOKA TADAYUKI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
摘要： PURPOSE:To improve the integration density of a semiconductor integrated circuit device, by constituting an element isolating groove surrounding the base region of a bipolar transistor, and constituting a base electrode, which is connected to a base region in a self-aligning manner. CONSTITUTION:A collector electrode, a base electrode and an emitter electrode 13 are formed. An element isolating groove 8A surrounding a base region B of a bipolar transistor is constituted. A lead-out base electrode 8D, which is connected to the base region B in a self-aligning manner, is formed at the shoulder part of the element isolating groove 8A. Thus the area of the base region B can be reduced. The area of a first element isolating region 8 can be also reduced. The integration density of a semiconductor integrated circuit device can be improved. An embedded collector region 3 is formed so that it is in contact with an insulating film 8B of the first element isolating region 8, whose dielectric constant is small. Therefore, parasitic capacitance is decreased, and the operating speed of the semiconductor integrated circuit device can be made high.

5. 发明专利

JPS62298168A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62298168A
公开(公告)日：1987-12-25
申请号：JP14006686
申请日：1986-06-18
申请人： HITACHI LTD
发明人： TAKAHASHI TAKAHIKO , KASAHARA OSAMU , TANEOKA TADAYUKI
IPC分类号： H01L29/43 , H01L21/28
摘要： PURPOSE:To prevent deposition of an Si single crystal at the time of heat treatment and to prevent the increase in electric resistance, by providing a silicon nitride film between an electrode comprising Al, or metal, whose main component is Al, and an active region. CONSTITUTION:In a P-type Si substrate 1, a source 2 and a drain 3, which are two N-type active regions, are separately formed. An insulating film 4 comprising SiO2 is deposited thereon. Opening parts 6 and 6a are formed at places on the source 2 and the drain 3 in the insulating film 4. Ohmic electrodes 7 and 7a are formed through silicon nitride films 8 and 8a. The electrodes 7 and 7a are formed with Al or metal, whose main component is Al. A gate electrode 5 is also formed on the insulating film 4. Even if high temperature heat history is received, an Si single crystal is not deposited between the electrode and the substrate, and the increase in electric resistance can be prevented.

6. 发明专利

JPS61112351A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS61112351A
公开(公告)日：1986-05-30
申请号：JP23312084
申请日：1984-11-07
申请人： Hitachi Ltd
发明人： TANEOKA TADAYUKI
IPC分类号： H01L21/3205 , H01L21/82 , H01L23/52
摘要： PURPOSE:To reduce a temperature difference between an acceptable block and a defective block due to heat generation in a circuit on the operation of a pellet, and to prevent the generation of stress between both blocks by connecting even the defective block to a power supply wiring. CONSTITUTION:A plurality of circuit blocks 9 are electrically connected mutu ally to a wafer, thus forming a full wafer LSI 2. Even a defective block 10 is connected electrically to a power supply wiring 14 regarding a power supply electrode 13a among electrode 13 shaped onto the upper surface of an silicon substrate 12, thus supplying currents. Signal electrodes disposed in the left direction of the power supply electrode 13a is connected electrically to a second wiring 14a in an acceptable block 11, but they are unnecessitated in the defective block, thus resulting in no electrical connection.
摘要翻译：目的：为了减少由于在芯片的操作中电路中的发热引起的可接受的块和缺陷块之间的温度差，并且通过将缺陷块连接到电源布线来防止两个块之间的应力产生。构成：多个电路块9多个电连接到晶片上，从而形成整个晶圆LSI 2.即使有缺陷块10与电源配线14电连接，电源线13形成在电极13之间，硅衬底12的上表面，从而提供电流。设置在电源电极13a的左方向上的信号电极在可接受的块11中电连接到第二布线14a，但是在缺陷块中不必要地发生电连接。

7. 发明专利

JPS60245276A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60245276A
公开(公告)日：1985-12-05
申请号：JP10046284
申请日：1984-05-21
申请人： HITACHI LTD
发明人： TANEOKA TADAYUKI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/732
摘要： PURPOSE:To enable the improvement in carrier mobility of a diffused layer, e.g. fT of a bi-polar transistor and in operating speed by a method wherein a diffused layer and an active region are formed so as to make each of the two contain only susceptors or doners. CONSTITUTION:After a P type impurity is selectively ion-implanted to an epitaxial layer 4 in the part serving as the base region, a P type base region 7 is formed by heat-treatment. A groove 13 is formed down to a desired emitter depth in the base region 7. An N type region 8 of high concentration is formed only in the groove 13 by growing single crystal Si containing a high concentration of N type impurity. This manner enables the formation of the emitter region 8 only with donars and leads the electric impurity concentration in the emitter region 8 to a required emitter-impurity-concentration without an increase in chemical impurity concentration. Therefore, the chemical impurity concentration decreases, and the mobility in the emitter region 8 and fT of the transistor increase, resulting in speed-up in switching action.

8. 发明专利

JPS6473718A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6473718A
公开(公告)日：1989-03-20
申请号：JP22952587
申请日：1987-09-16
申请人： HITACHI LTD
发明人： TANEOKA TADAYUKI
IPC分类号： H01L21/8222 , H01L21/027 , H01L21/30 , H01L27/06
摘要： PURPOSE:To prevent any defective resolution of resist due to a step on the surface of a substrate from occurring by a method wherein the step for alignment in the photolithographic process performed after epitaxial formation is formed only on an alignment part (a) on the substrate. CONSTITUTION:An insulating film 2 is formed on the surface of a semiconductor substrate 1 by thermal oxidation; another insulating film 3 is formed on the film 2 by CVD process; and the other insulating film 4 capable of selectively etching the insulating film 3 is formed. Resist patterns 5 in specific shapes corresponding to the shapes of buried layers 7 are formed on the insulating film 4. Then, openings 4a, 4b are made using said patterns 5 as masks to form a resist pattern 6 for the opening 4a. The other opening 3a is made using the pattern 6 and the insulating film 4 as masks. Finally, after forming the layers 7, the insulating films 4, 3, 2 are etched away to form a step 8 for alignment on the surface of the exposed substrate 1.

9. 发明专利

JPS62150883A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62150883A
公开(公告)日：1987-07-04
申请号：JP29052985
申请日：1985-12-25
申请人： HITACHI LTD
发明人： TAKAHASHI TAKAHIKO , TANEOKA TADAYUKI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
摘要： PURPOSE:To improve the uniformity of the current amplification factors hFE of a plurality of bipolar transistors by forming a barrier layer made of a silicon nitride film having preferable controllability thicker than a silicon oxide film on the emitter regions of the bipolar transistors. CONSTITUTION:An emitter electrode 9 made of a polycrystalline silicon layer is provided on an N type emitter region. The electrode 9 is electrically connected through a hole 10 formed by selectively removing an insulating film 8 with the region 1. A silicon nitride film 11 used mainly as a barrier layer of holes is interposed between the electrode 9 and the region 1. The thickness of the silicon nitride film is extremely reduced to approx. 10-20Angstrom . Thus, since the holes pass the film 11, they need energy larger than electrons. Accordingly, the current amplification factor hFE of a bipolar transistor can be enhanced by providing the film 11 as a barrier layer.

10. 发明专利

JPS60198748A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS60198748A
公开(公告)日：1985-10-08
申请号：JP5421384
申请日：1984-03-23
申请人： HITACHI LTD
发明人： KAWAJI MOTONORI , TANEOKA TADAYUKI , TAKAKURA TOSHIHIKO , KURODA SHIGEO
IPC分类号： H01L21/822 , H01L21/331 , H01L21/76 , H01L21/764 , H01L21/82 , H01L27/04 , H01L27/118 , H01L29/73 , H01L29/732
摘要： PURPOSE:To execute a design for a wiring and the variation of the wiring easily by filling the inside of a U-shaped isolation region for isolating elements with a low-resistance conductive material, utilizing the conductive material as a power supply line, adding one wiring layer and forming a jumper line. CONSTITUTION:An N type buried layer 2 and an N type epitaxial layer 3 are grown on a semiconductor substrate 1, and an oxide film 4 and a nitride film 5 are shaped on the epitaxial layer 3. The films 4, 5 are removed partially to form U-shaped grooves 7a, 7b. Channel stopper layers 8 and insulating films 9 are shaped, and nitride films 11 are formed inside the U-shaped grooves 7a, 7b. The insides of the U-shaped grooves 7a, 7b are filled with polysilicon 12. Polysilicon 12 in the U-shaped groove as a section into which a wiring for a power supply mush be buried is removed, and the U-shaped groove is filled with aluminum 21. Aluminum wirings 24, inter-layer insulating films 25, aluminum wirings 26, inter-layer insulating films 27 and aluminum wirings 28 are shaped on the whole surface and lastly a passivation film 29 is formed on the whole surface.

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