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1. 发明专利

JPS58155721A METHOD OF DIFFUSING IMPURITY INTO SEMICONDUCTOR 失效
公开(公告)号：JPS58155721A
公开(公告)日：1983-09-16
申请号：JP3072483
申请日：1983-02-28
申请人： HITACHI LTD
发明人： TATEFURU NOBORU , INABA KEIZOU , TAKEI ICHIROU
IPC分类号： H01L21/223 , H01L21/00 , H01L21/22
摘要： PURPOSE:To make it possible to obtain diffused layers without any variations between wafers, by depositing an impurity on the surfaces of semiconductor wafers in a decompressed or vacuum state, and heat-treating the semiconductor wafers. CONSTITUTION:Impurity sources 1 and Si wafers 2 are stood on a jig 3 so as to face each other, respectively. The jig 3 is placed in a vessel 4, which is decompressed or evacuated and hermeticaly sealed. The hermetically sealed vessel 4 is housed in a quartz tube 6 in a heated heating furnace 5 and heated. In this case, since the space between the adjacent wafer 2 and impurity source 1 is in a vacuum state, the variations in impurity concentration between the surfaces of the wafers 2 is exceedingly small. The wafers thus subjected to the deposition diffusion are taken out of the vacuum vessel, and the deposited glass layers are etched. Thereafter, a surface oxidation and an elongation diffusion are effected on heating in an atmosphere which is not reduced in pressure. Thus, it is possible to obtain semiconductor devices having reduced variations.

2. 发明专利

JPS57192019A CONTINUOUS HEAT TREATMENT DEVICE 失效
公开(公告)号：JPS57192019A
公开(公告)日：1982-11-26
申请号：JP7653981
申请日：1981-05-22
申请人： HITACHI LTD
发明人： INABA KEIZOU , TAKEI ICHIROU , YOSHIDA KIYOSHI
IPC分类号： H01L21/673 , H01L21/00 , H01L21/22 , H01L21/677
摘要： PURPOSE:To subject uniform heat treatment to a material to be treated by continuously passing the material in a reaction tube by a transfer mechanism using a slot loosely fitting the material. CONSTITUTION:A heater 3 covered with a cover 2 consisting of a heat insulating material is arranged onto the outer circumferential section of the cylindrical reaction tube 1, both ends thereof are opened. Three shafts 7 for carrying are mounted into the reaction tube 1 in the longitudinal direction, and feed screws 8 are formed to the outer circumferences of the shafts 7. The fringe sections of semiconductor wafers 10 are loosely fitted into the slots 9 of the feed screws 8, the shafts 7 are turned by a driving source 11, and the wafers 10 are transferred to an outlet section 6 from the inlet section 5 of the reaction tube 1 at every one sheet. Accordingly, since the wafers 10 pass through a treating chamber 4 in the reaction tube 1 at every one sheet, the wafers are treated continuously while being thermally treated uniformly.

3. 发明专利

JPS52156782A PLANETARY JIG FOR VACUUM EVAPORATION 失效
公开(公告)号：JPS52156782A
公开(公告)日：1977-12-27
申请号：JP7314976
申请日：1976-06-23
申请人： HITACHI LTD
发明人： KOYAMA HACHIROU , TAKEI ICHIROU
IPC分类号： C23C14/50 , H01L21/285
摘要： PURPOSE:To prevent the sticking of the evaporated substance to the back surface of the back surface of the material to be evaporated (e.g. semiconductor wafer) due to goinground of the evaporated substance, by arranging the shutter plate formed so as to cover the groove at the circumferential part of the substrate while conforming to the groove part.

4. 发明专利

JPS5295975A PREVENTION OF LEAK OF IMPURITY IN MANUFACTURING SEMICONDUCTOR UNIT 失效
公开(公告)号：JPS5295975A
公开(公告)日：1977-08-12
申请号：JP1226176
申请日：1976-02-09
申请人： HITACHI LTD
发明人： KITAHARA TOSHIAKI , TAKEI ICHIROU , TAKAHASHI MOTOHIRO
IPC分类号： H01L21/22 , H01L21/31
摘要： PURPOSE:To prevent leak of impurity in single surface collector diffusion by forming at least two layers of SiO2 film and forming the first layer at a temperature which will not cause diffusion of the impurity.

5. 发明专利

JPS57121223A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS57121223A
公开(公告)日：1982-07-28
申请号：JP638481
申请日：1981-01-21
申请人： Hitachi Ltd
发明人： SHIMURA ISAO , SHIMIZU SHIYUUICHI , NISHIYAMA MASAMI , TAKEI ICHIROU
IPC分类号： H01L23/522 , H01L21/28 , H01L21/331 , H01L21/768 , H01L29/41 , H01L29/73
CPC分类号： H01L21/28
摘要： PURPOSE:To prevent invasion of contaminations from the circumferential edge of the electrode part and to prevent deterioration of characteristic of a semiconductor device by a method wherein the device is constituted as to make a passivation film to bury the interval between the inside circumferential face of a window for contact of electrode and the outside circumferential face of the electrode. CONSTITUTION:The interval between the outside circumferential lower edge of the emitter electrode 6 and the inside circumferential lower edge of the window 10 for contact of electrode is made to about 0.5mum, and the inside circumferential face of the window 10 for contact of electrode and the outside circumferential face of the emitter electrode 6 facing thereto are made to have structure extending toward the upper part. As a result, the passivation film 7 can be formed continuously without generating disconnection at a step part, the film reaches surely the interval between the inside circumferential face of the window 10 for contact of electrode and the outside circumferential face of the emitter electrode 6, the exposed emitter region is covered completely. Accordingly contamination from the outside can be prevented.
摘要翻译：目的：为了防止从电极部分的周缘侵入污染物并防止半导体器件的特性劣化，其中该器件被构造成制造钝化膜以将间隔埋在电极接触的窗口和电极的外周面。构成：将发射电极6的外周下缘与电极接触用窗10的内周下缘之间的间隔设定为约0.5μm，电极接触用窗10的内周面使发射电极6的面向其的外周面具有朝向上部延伸的结构。结果，可以连续地形成钝化膜7，而不会在台阶部产生断开，薄膜可靠地确保用于电极接触的窗口10的内周面与发射电极6的外周面之间的间隔，暴露的发射极区域被完全覆盖。因此可以防止来自外部的污染。

6. 发明专利

JPS55113321A JIG FOR HEAT TREATMENT 失效
公开(公告)号：JPS55113321A
公开(公告)日：1980-09-01
申请号：JP1980479
申请日：1979-02-23
申请人： HITACHI LTD
发明人： SHIMURA ISAO , TAKEI ICHIROU
IPC分类号： H01L21/31 , H01L21/22 , H01L21/316
摘要： PURPOSE:To prevent deformation in long hours' processing at high temperature by connecting groove-fitted jigs, made of quartz and supporting a wafer, by means of jigs made of Si or SiC. CONSTITUTION:Quartz rods 1a, 1b, ... are provided with grooves 3 for supporting a wafer. Arc-shaped supporting jigs 2a, 2b, ... are made of Si or SiC for connecting and supporting the quartz jigs. By this structure, no deformation occurs on the jigs as a whole even if they are used at high temperature and in long hours. Since the groove-fitted rods are made of quartz, no small pieces stick to the wafer as in the case of Si rods, so that damage to the mask can be prevented in photo-etching.

7. 发明专利

JPS5339060A LOT NUMBER MARKING METHOD TO WAFERS 失效
公开(公告)号：JPS5339060A
公开(公告)日：1978-04-10
申请号：JP11314776
申请日：1976-09-22
申请人： HITACHI LTD
发明人： TAKEI ICHIROU , TANAKA KOUSUKE
IPC分类号： H01L21/02 , H01L21/302 , H01L21/306
摘要： PURPOSE:To make wafer creaking less as compared to mechanical numbering by marking a lot number on the material to be shielded of ultraviolet rays, bonding this to a glass mask, superposing the mask on a wafer coated with photoresist. exposing and developing the mask, thereafter etching the wafer leaving the lot number on the wafer.

8. 发明专利

JPS58212125A Jig for heat treatment 失效
标题翻译： JIG用于热处理
公开(公告)号：JPS58212125A
公开(公告)日：1983-12-09
申请号：JP9312582
申请日：1982-06-02
申请人： Hitachi Ltd
发明人： KITAHARA TOSHIAKI , TAKEI ICHIROU
IPC分类号： C23C16/458 , H01L21/205 , H01L21/31
CPC分类号： C23C16/4587 , H01L21/02532 , H01L21/0262
摘要： PURPOSE:To obtain the heat treatment jig enabled to unify on the whole rgion of a wafer film thickness and quality of a film to be generated by a method wherein thermal capacity of a susceptor consisting of a quartz plate larger than the wafer is utilized. CONSTITUTION:Thickness of the susceptor 10 is made to from several times to ten several times of thickness of the wafer 1 to enlarge thermal capacity, and is used as a buffer to make temperature variation received by the wafer 1 as to become gently at heating time when the heat treatment jig 8 is inserted in a core tube, and at cooling time when the jig is taken out from the core tube. Moreover, to make the buffer effect to the maximum, gaps 13 between nails 12 and a holding face 11 are made small, and the wafer 1 is made as to adhere closely to the holding face 11. Moreover, the circumferential edge part of the susceptor 10 is protruded further than the circumferential edge part of the wafer 1 so as to make the circumferential edge part of the wafer 1 to generate temperature variation the same with the central part, and when the wafer comes in contact with the temperature at the inside and the outside of the core tube, the structure is designed such that the circumferential edge of the wafer 1 only is inhibited to follow sensitively the temperature thereof. A poly-silicon film is formed on the surface of the wafer 1 according to the low pressure CVD method using the heat treatment jig 8 like this, and the respective wafers are porduced with unified film thickness, film quality at the respective parts of the wafer.
摘要翻译：目的：获得能够通过利用由比晶片大的石英板构成的基座的热容量的方法来生成晶片膜厚度和膜质量的整体的热处理夹具。构成：将基座10的厚度设定为晶片1厚度的几倍至十几倍，以增加热容量，并且用作缓冲器，以使由晶片1接收的温度变化在加热时变得温和当热处理夹具8插入芯管中时，以及当夹芯从芯管中取出时的冷却时间。此外，为了使缓冲效果达到最大，钉子12和保持面11之间的间隙13变小，并且使晶片1紧密地附着在保持面11上。此外，基座的周缘部 10比晶片1的周缘部分突出，使得晶片1的周缘部分产生与中心部分相同的温度变化，并且当晶片与内部的温度接触时，以及芯管的外侧，结构被设计成使得晶片1的圆周边缘仅被抑制以敏感地跟随其温度。使用这样的热处理夹具8，根据低压CVD法在晶片1的表面上形成多晶硅膜，并且各晶圆均匀地成膜，晶圆各部分的膜质量。

9. 发明专利

JPS57210669A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS57210669A
公开(公告)日：1982-12-24
申请号：JP9380981
申请日：1981-06-19
申请人： HITACHI LTD
发明人： YANAGI YOSHIKAZU , TAKEI ICHIROU , INABA KEIZOU
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72
摘要： PURPOSE:To improve the characteristic and reliability of a transistor by forming an emitter by implanting impurity ions of perpendicular direction. CONSTITUTION:An imprutiy is introduced to the surface of an N type Si substrate 1 with an oxidized film 3 as a mask to form a base region 2, and an emitter forming hole is formed at the film 3. After a thin oxidized film 7 is then formed on the surface of the hole, an ion beam is implanted at an incident angle of 90 deg. with respect to the surface of the substrate, and phosphorous is injected. Then, an N type emitter region 5 is formed by thermal diffusion, and a phosphorous glass layer 6 is simultaneously formed on the film 3. Thereafter, a light etching is performed, the phosphorous-doped oxidized film on the surface of emitter is removed, and an emitter aluminum electrode 8 is formed. In this manner, a transistor in which no glass layer is formed on the surface of the wall of the hole of the emitter can be obtained.

10. 发明专利

JPS5419650A PRODUCTION OF SEMICONDUCTOR DEVICES 失效
公开(公告)号：JPS5419650A
公开(公告)日：1979-02-14
申请号：JP8427077
申请日：1977-07-15
申请人： HITACHI LTD
发明人： KOYAMA HACHIROU , TAKEI ICHIROU
IPC分类号： H01L21/52 , H01L21/283
摘要： PURPOSE:To simplify fusion-welding operation and make possible automatic fusionwelding without applying rubbing at the time of fusion-weldingof semiconductor pellets by exposing an Au-rich surface through etching.

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