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1. 发明专利

IT8322738D0 未知
公开(公告)号：IT8322738D0
公开(公告)日：1983-09-01
申请号：IT2273883
申请日：1983-09-01
申请人： HITACHI LTD
发明人： KUNIMI NOBUO , SHIMIZU KOICHI , SUZUKI TOSHIRO
IPC分类号： H03F1/30 , H03F3/30 , H03F3/45
摘要： A differential amplifier formed of MISFETs includes a differential amplification stage and a pair of cascade amplification stages which receive outputs from the differential amplification stage. In each of the cascade amplification stages, an amplifying MISFET which receives an input signal at its source has a channel conductivity of opposite type to that of the differential input MISFETs of the differential amplification stage. The differential amplifier with this construction has good frequency characteristics. Since the pair of cascade amplification stages make the currents taken from a pair of outputs from the differential amplification stage equal to each other, the operating balance of the differential amplification stage is not affected. The differential amplifier further includes a feedback circuit which detects the operating points of these cascade amplification stages by referring to the outputs of the cascade amplification stages, and generates a control voltage by comparing the operating points thus detected with a reference potential. The control voltage is fed back to the gates of the amplifying MISFETs in each cascade amplification stage. As a result, the operating point of each cascade amplification stage can be stabilized irrespective of variations in the characteristics of the MISFETs or the changes of their characteristics.

2. 发明专利

FR2532797B1 未知
公开(公告)号：FR2532797B1
公开(公告)日：1990-11-30
申请号：FR8312881
申请日：1983-08-04
申请人： HITACHI LTD
发明人： KUNIMI NOBUO , SHIMIZU KOICHI , SUZUKI TOSHIRO
IPC分类号： H03F1/30 , H03F3/30 , H03F3/45
摘要： A differential amplifier formed of MISFETs includes a differential amplification stage and a pair of cascade amplification stages which receive outputs from the differential amplification stage. In each of the cascade amplification stages, an amplifying MISFET which receives an input signal at its source has a channel conductivity of opposite type to that of the differential input MISFETs of the differential amplification stage. The differential amplifier with this construction has good frequency characteristics. Since the pair of cascade amplification stages make the currents taken from a pair of outputs from the differential amplification stage equal to each other, the operating balance of the differential amplification stage is not affected. The differential amplifier further includes a feedback circuit which detects the operating points of these cascade amplification stages by referring to the outputs of the cascade amplification stages, and generates a control voltage by comparing the operating points thus detected with a reference potential. The control voltage is fed back to the gates of the amplifying MISFETs in each cascade amplification stage. As a result, the operating point of each cascade amplification stage can be stabilized irrespective of variations in the characteristics of the MISFETs or the changes of their characteristics.

3. 发明专利

GB2126817A DIFFERENTIAL AMPLIFIER 未知
公开(公告)号：GB2126817A
公开(公告)日：1984-03-28
申请号：GB8322913
申请日：1983-08-25
申请人： HITACHI LTD
发明人： KUNIMI NOBUO , SHIMIZU KOICHI , SUZUKI TOSHIRO
IPC分类号： H03F1/30 , H03F3/30 , H03F3/45 , H03F3/345
摘要： A differential amplifier formed of MISFETs includes a differential amplification stage and a pair of cascade amplification stages which receive outputs from the differential amplification stage. In each of the cascade amplification stages, an amplifying MISFET which receives an input signal at its source has a channel conductivity of opposite type to that of the differential input MISFETs of the differential amplification stage. The differential amplifier with this construction has good frequency characteristics. Since the pair of cascade amplification stages make the currents taken from a pair of outputs from the differential amplification stage equal to each other, the operating balance of the differential amplification stage is not affected. The differential amplifier further includes a feedback circuit which detects the operating points of these cascade amplification stages by referring to the outputs of the cascade amplification stages, and generates a control voltage by comparing the operating points thus detected with a reference potential. The control voltage is fed back to the gates of the amplifying MISFETs in each cascade amplification stage. As a result, the operating point of each cascade amplification stage can be stabilized irrespective of variations in the characteristics of the MISFETs or the changes of their characteristics.

4. 发明专利

FR2532797A1 未知
公开(公告)号：FR2532797A1
公开(公告)日：1984-03-09
申请号：FR8312881
申请日：1983-08-04
申请人： HITACHI LTD
发明人： KUNIMI NOBUO , SHIMIZU KOICHI , SUZUKI TOSHIRO
IPC分类号： H03F1/30 , H03F3/30 , H03F3/45
摘要： A differential amplifier formed of MISFETs includes a differential amplification stage and a pair of cascade amplification stages which receive outputs from the differential amplification stage. In each of the cascade amplification stages, an amplifying MISFET which receives an input signal at its source has a channel conductivity of opposite type to that of the differential input MISFETs of the differential amplification stage. The differential amplifier with this construction has good frequency characteristics. Since the pair of cascade amplification stages make the currents taken from a pair of outputs from the differential amplification stage equal to each other, the operating balance of the differential amplification stage is not affected. The differential amplifier further includes a feedback circuit which detects the operating points of these cascade amplification stages by referring to the outputs of the cascade amplification stages, and generates a control voltage by comparing the operating points thus detected with a reference potential. The control voltage is fed back to the gates of the amplifying MISFETs in each cascade amplification stage. As a result, the operating point of each cascade amplification stage can be stabilized irrespective of variations in the characteristics of the MISFETs or the changes of their characteristics.

5. 发明专利

DE3331626A1 未知
公开(公告)号：DE3331626A1
公开(公告)日：1984-03-08
申请号：DE3331626
申请日：1983-09-01
申请人： HITACHI LTD
发明人： KUNIMI NOBUO , SHIMIZU KOICHI , SUZUKI TOSHIRO
IPC分类号： H03F1/30 , H03F3/30 , H03F3/45
摘要： A differential amplifier formed of MISFETs includes a differential amplification stage and a pair of cascade amplification stages which receive outputs from the differential amplification stage. In each of the cascade amplification stages, an amplifying MISFET which receives an input signal at its source has a channel conductivity of opposite type to that of the differential input MISFETs of the differential amplification stage. The differential amplifier with this construction has good frequency characteristics. Since the pair of cascade amplification stages make the currents taken from a pair of outputs from the differential amplification stage equal to each other, the operating balance of the differential amplification stage is not affected. The differential amplifier further includes a feedback circuit which detects the operating points of these cascade amplification stages by referring to the outputs of the cascade amplification stages, and generates a control voltage by comparing the operating points thus detected with a reference potential. The control voltage is fed back to the gates of the amplifying MISFETs in each cascade amplification stage. As a result, the operating point of each cascade amplification stage can be stabilized irrespective of variations in the characteristics of the MISFETs or the changes of their characteristics.

6. 发明专利

JPH0565896B2 失效
公开(公告)号：JPH0565896B2
公开(公告)日：1993-09-20
申请号：JP3856684
申请日：1984-03-02
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： IWAKI SHINICHI , TAKEMURA TETSUO , SHIMIZU KOICHI , TAKAHASHI TATSURO , ARAGAKI NAOYA , IWASE YASUMASA
IPC分类号： G06F13/28

7. 发明专利

JPH0541075A MAGNETIC RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH0541075A
公开(公告)日：1993-02-19
申请号：JP22115691
申请日：1991-08-07
申请人： HITACHI LTD
发明人： KAWAKAMI HIROJI , MORIBE YOSHIHIRO , SHIMIZU KOICHI
IPC分类号： G11B5/11 , G11B5/33 , G11B19/00 , G11B25/04 , G11B33/14
摘要： PURPOSE:To prevent the damage of the magnetic disk memory device by the electric discharge generated between a magneto-resistance effect type head and a conductive magnetic recording medium by the high-frequency radio waves or magnetic fields applied to the device from the outside. CONSTITUTION:The main part of the magnetic disk memory device including a conductive magnetic disk 10, an MR magnetic head element 31, a revolving shaft 56 for driving the disk, a head driving device 57, a preamplifier 62, etc., is enclosed with an outside box 51 and cap 52 consisting of a metal having at least >=0.01mm thickness, by which the influence of the above-mentioned radio waves and magnetic fields is decreased. A liquid metal is interposed in a sliding current collector 58 making an electrical connection between the revolving shaft 56 and the outside box to decrease a contact potential difference. The induced voltage between the head and the recording medium is decreased in this way and the discharge therebetween is prevented.

8. 发明专利

JPH0269098A TIME SLOT ORDER PRESERVING DEVICE AND COMMUNICATION SYSTEM PROVIDED THEREWITH 失效
公开(公告)号：JPH0269098A
公开(公告)日：1990-03-08
申请号：JP22031088
申请日：1988-09-05
申请人： HITACHI LTD
发明人： SHIMIZU KOICHI
IPC分类号： H04Q11/04
摘要： PURPOSE:To improve the understanding rate to the multidimensional call of a communication system by providing a time slot order preserving device to an exchange node constituted of a single buffer and restoring the order of time slots by alternately switching the writing operations of two time division switches at every frame. CONSTITUTION:At the time of processing such a call as a double call, two time slots A and B are housed as shown by the in-highway IH, since the number of delayed frames informed to an exchange node 11d is (0.1). In the n-th frame, the content of the in-highway is written in a channel switch is and, at the same time, the written content is read out. At the same time, the content written in a channel switch 1b is read out in the (n-1)-th frame. In the (n+1)-th frame, operations of channels switches 1a and 1b are inverted from each other. Therefore, the time slot order preservation in the same frame disturbed by an exchange node constituted of a single buffer can be restored completely and the understanding rate to the multidimensional call of a communication system can be improved.

9. 发明专利

JPS61236238A METHOD FOR TRANSFERRING KEY 失效
公开(公告)号：JPS61236238A
公开(公告)日：1986-10-21
申请号：JP7641885
申请日：1985-04-12
申请人： HITACHI LTD
发明人： SHIMIZU KOICHI , TAKEMURA TETSUO , GOHARA SHINOBU , IWAKI SHINICHI
IPC分类号： H04L9/06 , H04L9/00 , H04L9/08 , H04L9/14
摘要： PURPOSE:To prevent interception of ciphered talking information by transferring the ciphered communication information through a channel, transferring a key required for decoding through a common line signal line to separate the transfer route for a message and the key. CONSTITUTION:A sender exchange 1 ciphers the communication information and the result is transferred to an incoming exchange 7 via channels 18, 19 set by link by link. Further, the key required for decoding is transferred from the exchange 1 to the exchange 7 in a way of end-to-end via common line signal paths 15-17 and a signal relay station 12. Then the talking information from a terminal device 13 is ciphered at a deciphering device 2i by using the key and transferred to the exchange 7 via a channel switch 3, the channel 18, an exchange 6 and the channel 19. The ciphered communication information is decoded by a deciphering device 9i via the channel switch 8 by using the key and the result is transferred to a terminal 14. Further, the talking information from the terminal 14 is ciphered by the deciphering device 9i by using the key, transferred to the exchange 1 and decoded by a deciphering device 2i by the key and the result is transferred to the terminal device 13.

10. 发明专利

JPS61194620A THIN FILM MAGNETIC HEAD 失效
公开(公告)号：JPS61194620A
公开(公告)日：1986-08-29
申请号：JP3266385
申请日：1985-02-22
申请人： HITACHI LTD
发明人： SHIMIZU KOICHI , DAITO HIROSHI , KARAKAMA YOSHIAKI
IPC分类号： G11B5/31 , G11B5/39
摘要： PURPOSE:To execute the high density recording under optimum conditions of recording and reproducing effeciency by sharing some part of one magnetic layer of the 1st magnetic circuit, opening medium facing ends of a medium and providing the 2nd reproducing magnetic converter constituted with the 2nd magnetic circuit in-cluding a magneto resistance effect element structure having one connected end inside. CONSTITUTION:A base insulating material 2 is formed on a substrate 1 and then the magnetic layer 3 is formed. Moreover the MR element structure 4 is formed at the medium facing end 11 of the magnetic layer 3, and then a magnetic layer 5 is formed. Gaps 13a and 13b are formed between the magnetic layers 3 and 5 and the MR element structure 4 and connected to the end which does not face the medium. Said magnetic layers 3 and 5 comprise one end of a recording magnetic circuit 10. Then a gap 6 is built up and thereon a conductive coil 6 is formed. Next a magnetic layer 8 is formed so that the magnetic layer 5 and the medium facing end 11 can comprise the gap 6 and the layer 8 can connect to the magnetic layer 5 at its other end. The element group is cut, and the medium facing end 11 is processed, whereby the recording magnetic circuit 11 with the magnetic gap 6 and the MR element structure 4 form integrally a thin film magnetic head.

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