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1. 发明专利

DE3856370T2 未知
公开(公告)号：DE3856370T2
公开(公告)日：2000-06-21
申请号：DE3856370
申请日：1988-07-14
申请人： HITACHI LTD
发明人： SAKURAI YOSHITO , GOHARA SHINOBU , OHTSUKI KENICHI , MORI MAKOTO , HORIKI AKIRA , KATO TAKAO , KUWAHARA HIROSHI
IPC分类号： H04L12/54 , H04L12/70 , H04L12/933 , H04L12/947 , H04Q11/04
摘要： A switching system is disclosed in which a plurality of incoming highways are multiplexed in time division cells that have arrived are written into a buffer memory (105), the cells thus written are read in an appropriate order, separated in a multiplex way and distributed among a plurality of outgoing highways thereby to perform an exchange operation. An FIFO (First In First Out) buffer (103) stores an empty address of the buffer memory (105). The address in busy state is controlled in a manner corresponding to the outgoing highways. When a cell is written in the buffer memory (105), the empty address is taken out of the data output of the FIFO buffer. When the cell is read of the buffer memory (105) the address already read is returned to the data input of the FIFO buffer by an idle address chain (103-104-105-104-110-103).

2. 发明专利

DE68928867T2 未知
公开(公告)号：DE68928867T2
公开(公告)日：1999-04-29
申请号：DE68928867
申请日：1989-07-19
申请人： HITACHI LTD
发明人： TORII YUTAKA HITACHI FUKIAGERY , MORI MAKOTO - - , GOHARA SHINOBU , OHTSUKI KENICHI , SAKURAI YOSHITO
IPC分类号： H04L49/111 , H04L12/56
摘要： The invention refers to an ATM (Asynchronous Transfer Mode) switching system including a self-routing switch performing switching operation for cells carrying communication information, a cell phase synchronizing circuit incorporated in each of ATM line termination apparatuses serving as interfaces between transmission paths and said self-routing switch for matching on a plurality of lines accommodated in said ATM switch the temporal phases of the cells contained in information streams outputted from line termination circuits serving for establishing physical matching of electrical conditions, traffic rate and others between said transmission lines and intra-system lines, comprising. cell phase detecting means for detecting positions of cells in said information streams (information bit row) on said intra-system lines; a cell synchronizing buffer connected to an incoming line by way of an isolating circuit and to an outgoing line by way of a selector circuit and including a plurality of buffer memories each having a capacity corresponding to at least one cell; a write control circuit for extracting a cell from the input information stream, selecting sequentially one of said plurality of buffer memories constituting said synchronizing buffer and writing the cells in said buffer one by one in the order of arrival; register means for indication the written states of said plurality of the buffer memories; and a read control circuit for controlling said selector circuit on the basis of the information in said register means to select the buffer memory to be next read out from the buffer memories storing the cells for thereby performing read control with a phase generated in synchronism with a system clock in common to all the line.

3. 发明专利

DE69124645D1 未知
公开(公告)号：DE69124645D1
公开(公告)日：1997-03-27
申请号：DE69124645
申请日：1991-08-13
申请人： HITACHI LTD
发明人： YANAGI JUNICHIROU , TAKASE AKIHIKO , KOZAKI TAKAHIKO , GOHARA SHINOBU
IPC分类号： H04Q3/00 , H04L47/22 , H04L47/43 , H04Q11/04 , H04L12/56
摘要： A traffic shaping method and circuit of a packet switching system in which input packets having a fixed length and multiplexed on a plurality of inputs (501-1...501-36) are multiplexed (11) to be delivered on any one of a plurality of outputs (502-1...502-36), connects the input packet to list structure using an address chain formed for each output, forms the list structure even for each line identifier provided in the packet, and assigns the identifier for each time slot of the output to take out the packet from the list structure, to prevent packets having the same identifier from being multiplexed and delivered to the output continuously.

4. 发明专利

DE68921685D1 未知
公开(公告)号：DE68921685D1
公开(公告)日：1995-04-20
申请号：DE68921685
申请日：1989-08-22
申请人： HITACHI LTD
发明人： KUNIMOTO MASAO , KASHIO JIRO , MORI MAKOTO , GOHARA SHINOBU
IPC分类号： H04L69/14 , H04L12/56 , H04Q11/04
摘要： A subscriber line signalling apparatus for use in an asynchronous mode communication system includes a switching circuit (30) having a plurality of input terminals (12-1 to 12-j) and a plurality of output terminals (13-1 to 13-k). The switching circuit (30) selectively communicates fixed length information packets to an adaptation processing unit (100). The adaptation processing unit (100) reassembles the fixed length packets to signalling frames, and transmits them to a frame processor (40).

5. 发明专利

CA2020244C PACKET SWITCH NETWORK FOR COMMUNICATION USING PACKET HAVING VIRTUAL CONNECTION IDENTIFIER VCI 未知
公开(公告)号：CA2020244C
公开(公告)日：1994-03-01
申请号：CA2020244
申请日：1990-06-29
申请人： HITACHI LTD
发明人： TANABE SHIROU , KAWAKITA KENJI , GOHARA SHINOBU
IPC分类号： H04L12/70 , H04Q3/42 , H04L12/56
摘要： In a packet network which includes a plurality of packet switching stations and in which a packet including in its header portion a VPI (Virtual Path Identifier) for identifying one of logical paths multipliexed on a transmission line and a VCI (Virtual Connection Identifier) for identifying one of logical connections multiplexed on one logical path is communicated between the switching stations, each switching station preliminarily designates a VCI to be given to a packet directed to that station when a logical connection is to be set up between that station and another station. When receiving an information packet from the other station, the each station makes access to header label conversion tables on the basis of a VCI included in the received packet to read internal routing information necessary for a packet switching operation and a VCI to be given to a packet to be delviered.

6. 发明专利

CA1291806C SWITCHING SYSTEM AND METHOD OF CONSTRUCTION THEREOF 未知
公开(公告)号：CA1291806C
公开(公告)日：1991-11-05
申请号：CA572002
申请日：1988-07-14
申请人： HITACHI LTD
发明人： SAKURAI YOSHITO , OHTSUKI KENICHI , GOHARA SHINOBU , MORI MAKOTO , HORIKI AKIRA , KATO TAKAO , KUWAHARA HIROSHI
IPC分类号： H04L12/54 , H04L12/70 , H04L12/933 , H04L12/947 , H04Q11/04 , H04L12/56
摘要： A switching system is disclosed in which a plurality of incoming highways are multiplexed in time division cells that have arrived are written into a buffer memory, the cells thus written are read in an appropriate order, separated in a multiplex way and distributed among a plurality of outgoing highways thereby to perform an exchange operation. An FIFO (First In First Out) buffer stores an empty address of the buffer memory. The address in busy state is controlled in a manner corresponding to the outgoing highways. When a cell is written in the buffer memory, the empty address is taken out of the data output of the FIFO buffer. When the cell is read of the buffer memory the address already read is returned to the data input of the FIFO buffer by an idle address chain.

7. 发明专利

CA2023446A1 PACKET COMMUNICATION METHOD, PACKET COMMUNICATION DEVICE AND PACKET SWITCHER 未知
公开(公告)号：CA2023446A1
公开(公告)日：1991-06-06
申请号：CA2023446
申请日：1990-08-16
申请人： HITACHI LTD
发明人： GOHARA SHINOBU , TORII YUTAKA
IPC分类号： H04Q3/00 , H04L47/43
摘要： In a packet communication method, a packet communication device, an input transmission frame of V (b/sec) consisting of a transmission overhead of VOH (b/sec) containing control information for transmission and a pay load of Vp (b/sec) of c (= a+b) bytes, the outer cell consisting of an information field of a b-byte length containing transmission data and a header field of an a-byte length containing a first control information for transmitting the information field (2, 21, 111, 202). The transmission overhead is removed from and a second control information is added to the input transmission frame (2, 201, 21, 23, 24, 25). The input transmission frame with the second control information and without the transmission overhead is converted to a plurality of inner cell trains of f (= b+j) bytes length, the inner cell trains consisting of an information field of a b-byte containing the transmission data and a second header field of j (= a+d) bytes consisting of the first control information and the second control information (where f x g = h x V, h is an integer or a fraction of an integer) (2, 203). Packets switching are performed on each inner cell (3). A plurality of inner cells are converted to an output transmission frame of V (b/sec) having the same format as the input transmission frame for transmission (4, 41, 204, 205, 206, 112).

8. 发明专利

DE69133547T2 未知
公开(公告)号：DE69133547T2
公开(公告)日：2007-09-06
申请号：DE69133547
申请日：1991-01-21
申请人： HITACHI LTD
发明人： TANABE SHIROU , SUZUKI TAIHEI , GOHARA SHINOBU
IPC分类号： H04L12/931 , H04Q11/04

9. 发明专利

DE69133547D1 未知
公开(公告)号：DE69133547D1
公开(公告)日：2006-10-26
申请号：DE69133547
申请日：1991-01-21
申请人： HITACHI LTD
发明人： TANABE SHIROU , SUZUKI TAIHEI , GOHARA SHINOBU
IPC分类号： H04L12/931 , H04Q11/04

10. 发明专利

DE69029755T2 未知
公开(公告)号：DE69029755T2
公开(公告)日：1997-08-07
申请号：DE69029755
申请日：1990-02-21
申请人： HITACHI LTD
发明人： KOZAKI TAKAHIKO , SAKURAI YOSHITO , GOHARA SHINOBU
IPC分类号： H04L49/9015 , H04Q11/04 , H04L12/56
摘要： A switching system for handling a plurality of cells, each cell including a header section and a data section, and for exchanging a communication message contained in the data section of the cell between a plurality of incoming highways and a plurality of outgoing highways according to the data contained in the header section of the cell, comprises a unit (1) for multiplexing said incoming highways in time division, a first memory (5) having addressable storage locations for storing cells received from the multiplexing unit, a unit (6) for demultiplexing and distributing data output from the first memory among a plurality of outgoing highways, a second memory (4) for storing an empty address of an empty storage location of the first memory, a unit (3) for controlling the write and read operations of the first memory in accordance with an empty address stored in the second memory used as write and read addresses, and a unit (20, 22, 24-27, 30-34) for detecting an error in at least one of the write address and read address.

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