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1. 发明专利

DE69029551T2 未知
公开(公告)号：DE69029551T2
公开(公告)日：1997-07-31
申请号：DE69029551
申请日：1990-08-16
申请人： HITACHI LTD
发明人： KAYAMA MASAHIRO , MOROOKA YARUO , OSHIGA TAKAYUKI , FUJIWARA KATSUHIRO
IPC分类号： G06F13/12 , G05B19/042 , G05B19/05 , G05B19/04
摘要： An input/output device (72) has a processor (202) which processes data strings received by the device (72). When a data string is received, it is passed to a serial interface (207) and a timing means (208). The serial interface (207) generates a signal which interrupts the existing processing by the processor (202) and causes the processor to start processing of the newly received data string. At the same time the timing means measures (208) the length of the data string and compares it with a predetermined length set by user-controllable data setting means (210). If the data string length reaches the predetermined length, the processor (202) is triggered to stop processing the new data string and to recommence the processing it was performing prior to interruption. The unprocessed part of the new data string is stored in a memory (205). In this way, urgent data strings, which are generally short, are processed rapidly and longer data strings are processed after the urgent data strings. It is not necessary for the data string to contain any information to identify its length.

2. 发明专利

ES2090194T3 未知
公开(公告)号：ES2090194T3
公开(公告)日：1996-10-16
申请号：ES91115867
申请日：1991-09-18
申请人： HITACHI LTD
发明人： OSHIGA TAKAYUKI , ITOH ATSUSHI , MATSUSHITA TSURUMASA , SUNAGA TSUTOMU
IPC分类号： G05B19/05
摘要： In a sequence program constructed by forming a ladder diagram on a display screen, an element corresponding to a minimum unit of the ladder diagram is arranged by a symbol element and a character element. Inputting and amending operations of the ladder diagram are performed by a first cursor (11) for designating each element and a second cursor (12) for designating the character element of the element designated by this first cursor (11).

3. 发明专利

DE3678271D1 未知
公开(公告)号：DE3678271D1
公开(公告)日：1991-04-25
申请号：DE3678271
申请日：1986-11-14
申请人： HITACHI LTD
发明人： FUJIWARA KATSUHIRO , OSHIGA TAKAYUKI , KASAHARA TOSHIRO
IPC分类号： G05B19/05
摘要： Data processing between selected I/O terminals (6a - 6n, 7a - 7n) is switched between processing by direct access to the I/O terminals and processing by indirect access through an image memory (41) having a one-to-one correspondence to the I/O terminals.

4. 发明专利

DE69121034T2 未知
公开(公告)号：DE69121034T2
公开(公告)日：1997-02-20
申请号：DE69121034
申请日：1991-09-18
申请人： HITACHI LTD
发明人： OSHIGA TAKAYUKI , ITOH ATSUSHI , MATSUSHITA TSURUMASA , SUNAGA TSUTOMU
IPC分类号： G05B19/05
摘要： In a sequence program constructed by forming a ladder diagram on a display screen, an element corresponding to a minimum unit of the ladder diagram is arranged by a symbol element and a character element. Inputting and amending operations of the ladder diagram are performed by a first cursor (11) for designating each element and a second cursor (12) for designating the character element of the element designated by this first cursor (11).

6. 发明专利

DE69029551D1 未知
公开(公告)号：DE69029551D1
公开(公告)日：1997-02-13
申请号：DE69029551
申请日：1990-08-16
申请人： HITACHI LTD
发明人： KAYAMA MASAHIRO , MOROOKA YARUO , OSHIGA TAKAYUKI , FUJIWARA KATSUHIRO
IPC分类号： G06F13/12 , G05B19/042 , G05B19/05 , G05B19/04
摘要： An input/output device (72) has a processor (202) which processes data strings received by the device (72). When a data string is received, it is passed to a serial interface (207) and a timing means (208). The serial interface (207) generates a signal which interrupts the existing processing by the processor (202) and causes the processor to start processing of the newly received data string. At the same time the timing means measures (208) the length of the data string and compares it with a predetermined length set by user-controllable data setting means (210). If the data string length reaches the predetermined length, the processor (202) is triggered to stop processing the new data string and to recommence the processing it was performing prior to interruption. The unprocessed part of the new data string is stored in a memory (205). In this way, urgent data strings, which are generally short, are processed rapidly and longer data strings are processed after the urgent data strings. It is not necessary for the data string to contain any information to identify its length.

7. 发明专利

DE69121034D1 未知
公开(公告)号：DE69121034D1
公开(公告)日：1996-08-29
申请号：DE69121034
申请日：1991-09-18
申请人： HITACHI LTD
发明人： OSHIGA TAKAYUKI , ITOH ATSUSHI , MATSUSHITA TSURUMASA , SUNAGA TSUTOMU
IPC分类号： G05B19/05
摘要： In a sequence program constructed by forming a ladder diagram on a display screen, an element corresponding to a minimum unit of the ladder diagram is arranged by a symbol element and a character element. Inputting and amending operations of the ladder diagram are performed by a first cursor (11) for designating each element and a second cursor (12) for designating the character element of the element designated by this first cursor (11).

10. 发明专利

JPH10229695A DUAL INVERTER 失效
公开(公告)号：JPH10229695A
公开(公告)日：1998-08-25
申请号：JP6146098
申请日：1998-03-12
申请人： HITACHI LTD
发明人： SATO KOICHI , YOSHIDA MASAO , OSHIGA TAKAYUKI , KUNII HIROSHI , ENDO TSUNEHIRO , HONMA SATOSHI
IPC分类号： F04D15/00 , H02M7/48 , H02P5/74 , H02P7/74
摘要： PROBLEM TO BE SOLVED: To realize simplicity, with downsizing and cost reduction by dispensing with an expensive controller for external attachment, provided in the superordinate place above a plurality of inverters to control a plurality of turbo machines. SOLUTION: This dual inverter is provided with two units of inverters INV1 and INV2, which correspond to each of the two units of turbo machines 5-1 and 5-2 provided in parallel, and each inverter has a built-in microcomputer, which takes in the load condition detection values of the turbo machines 5-1 and 5-2 and drive and control the turbo machines 5-1 and 5-2 connected to itself, according to the load condition detection value. Furthermore, they are connected with each other by a signal wiring S3 and communicate each operational state to each other, and decide the propriety of the operation for each inverter INV1 and INV2.

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