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1. 发明专利

DE3605152A1 未知
公开(公告)号：DE3605152A1
公开(公告)日：1986-09-11
申请号：DE3605152
申请日：1986-02-18
申请人： HITACHI LTD
发明人： ITOH ATSUSHI , OKAMURA MITSUSUKE , FUJIWARA KATSUHIRO , KASAHARA TOSHIRO
IPC分类号： G06F11/00 , G05B19/02 , G05B19/048 , G05B19/05 , G05B23/02 , G05B19/04
摘要： The states of the signals inputted to a programmable sequence controller or outputted from the programmable sequence controller are stored by a few scanning operations. A check is made to see if a combination of input and output signals which cannot be generated during one scanning operation in the normal operating mode exists in that memory content or not, thereby investigating causes of the occurrence of abnormalities.

2. 发明专利

ES2045209T3 未知
公开(公告)号：ES2045209T3
公开(公告)日：1994-01-16
申请号：ES89101802
申请日：1989-02-02
申请人： HITACHI LTD
发明人： KASAHARA TOSHIRO
IPC分类号： G06F3/02 , H03H17/02 , H03K5/08 , H03K5/1252 , H03K5/01
摘要： A filter circuit uses a reversible counter (31) to eliminate noise from an input signal (5) which changes between high and low levels. The input signal (5) is sampled in response to a clock signal (7) of selected frequency and the reversible counter is incremented by a sampled value at the high level and decremented by a sampled value at a low level. A hysteresis is built into the counting sequence by jumping the count by a predetermined value when the count is incremented over a first threshold value or decremented below a second threshold value.

3. 发明专利

DE68910379T2 未知
公开(公告)号：DE68910379T2
公开(公告)日：1994-04-14
申请号：DE68910379
申请日：1989-02-02
申请人： HITACHI LTD
发明人： KASAHARA TOSHIRO
IPC分类号： G06F3/02 , H03H17/02 , H03K5/08 , H03K5/1252 , H03K5/01
摘要： A filter circuit uses a reversible counter (31) to eliminate noise from an input signal (5) which changes between high and low levels. The input signal (5) is sampled in response to a clock signal (7) of selected frequency and the reversible counter is incremented by a sampled value at the high level and decremented by a sampled value at a low level. A hysteresis is built into the counting sequence by jumping the count by a predetermined value when the count is incremented over a first threshold value or decremented below a second threshold value.

4. 发明专利

DE68910379D1 未知
公开(公告)号：DE68910379D1
公开(公告)日：1993-12-09
申请号：DE68910379
申请日：1989-02-02
申请人： HITACHI LTD
发明人： KASAHARA TOSHIRO
IPC分类号： G06F3/02 , H03H17/02 , H03K5/08 , H03K5/1252 , H03K5/01
摘要： A filter circuit uses a reversible counter (31) to eliminate noise from an input signal (5) which changes between high and low levels. The input signal (5) is sampled in response to a clock signal (7) of selected frequency and the reversible counter is incremented by a sampled value at the high level and decremented by a sampled value at a low level. A hysteresis is built into the counting sequence by jumping the count by a predetermined value when the count is incremented over a first threshold value or decremented below a second threshold value.

5. 发明专利

DE3678271D1 未知
公开(公告)号：DE3678271D1
公开(公告)日：1991-04-25
申请号：DE3678271
申请日：1986-11-14
申请人： HITACHI LTD
发明人： FUJIWARA KATSUHIRO , OSHIGA TAKAYUKI , KASAHARA TOSHIRO
IPC分类号： G05B19/05
摘要： Data processing between selected I/O terminals (6a - 6n, 7a - 7n) is switched between processing by direct access to the I/O terminals and processing by indirect access through an image memory (41) having a one-to-one correspondence to the I/O terminals.

6. 发明专利

JPH05233476A 失效
公开(公告)号：JPH05233476A
公开(公告)日：1993-09-10
申请号：JP3029092
申请日：1992-02-18
申请人： HITACHI LTD
发明人： KASAHARA TOSHIRO
IPC分类号： G05B19/05 , G05B19/048 , G06F1/32 , G06F12/16
摘要： PURPOSE:To decrease the frequency of replacement of a backup battery and to extend the power failure guarantee time of backup operation by a large- capacity capacitor. CONSTITUTION:This programmable controller is provided with flip-flops 5-8 which hold data for operating the set coils 13a-16a of keep relays, flip-flops 40-43 which hold data for operating the reset coils of the keep relays, drivers 9-12 which drive the set coils 13a-16a according to the data set in the flip-flops, disconnection control means which use drivers 44-47 for driving the reset coils 13b-16b, and disconnecting means which uses the (a) contacts 13c-16c of the keep relays; and elements which are not used are disconnected from a power supply line 48 to reduce the load on the backup battery 1 or large-capacity capacitor.

7. 发明专利

JPS62145329A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPS62145329A
公开(公告)日：1987-06-29
申请号：JP28550285
申请日：1985-12-20
申请人： HITACHI LTD
发明人： FUJIWARA KATSUHIRO , OSHIGA TAKAYUKI , KASAHARA TOSHIRO , ITO ATSUSHI
IPC分类号： G06F9/48 , G05B19/05 , G06F9/46
摘要： PURPOSE:To operate a whole control system without any contradiction even when a process interruption is inputted in an optional state by setting a specific instruction which identifies the start of a relay sequence circuit and permitting the process interruption only when the instruction is read out. CONSTITUTION:When an interruption request is inputted from a process, a flip-flop 61 is set and when a signal which indicates a relay sequence head circuit is inputted from a control line (c) in this state, an interruption request a' to an arithmetic part 2 is outputted in the period. Then, when the control line (c) is reset, i.e. when an instruction except a relay sequence head circuit instruction is read, the flip-flop 61 is reset, so that the signal a' is never outputted after this resetting even if a signal (c) is inputted before a signal (a) is inputted. When an interruption acceptance mode select input (d) goes up to a level H, on the other hand, an AND gate 65 is opened on condition that the signal (c) and the output of the flip-flop 61 are both at the level H, so that the request a' is outputted through a OR gate 67.

8. 发明专利

JPS62117001A Input and output processing method for programmable sequence controller 失效
标题翻译：可编程序控制器的输入和输出处理方法
公开(公告)号：JPS62117001A
公开(公告)日：1987-05-28
申请号：JP25583585
申请日：1985-11-16
申请人： Hitachi Ltd
发明人： FUJIWARA KATSUHIRO , OSHIGA TAKAYUKI , KASAHARA TOSHIRO
IPC分类号： G05B19/05
CPC分类号： G05B19/054
摘要： PURPOSE: To secure the application of a programmable sequence controller to any type of controlled system by reducing satisfactorily the scan time of the sequence controller with use of an image memory and at the same time coping with a desired controlled system in a satisfactorily short answer time less than a single scan time.
CONSTITUTION: When the input/output control instructions (I/O set and reset instructions) are supplied through an arithmetic part 3, the control lines (set and reset lines) delivered from an instruction decoding part 31 are changed. The set and reset lines are connected to the set and reset inputs of a flip-flop 43 respectively at an input/output control part 4. Then the output of the flip-flop 43 is changed every time the IOC set and reset instructions emerge and then supplied to a data selector 42. Thus the selector 43 selects the external input/ output data given directly from an input part 6 and an output part 7 or the data given from an input/output image memory 41 and sends it to the part 3.
COPYRIGHT: (C)1987,JPO&Japio
摘要翻译：目的：通过使用图像存储器令人满意地减少序列控制器的扫描时间，同时在令人满意的短的应答时间内处理所需的受控系统，从而确保将可编程序控制器应用于任何类型的受控系统少于单次扫描时间。构成：通过运算部3供给输入输出控制指令（I / O设定和复位指令）时，从指令译码部31发送的控制线（置位和复位线）发生变化。设置和复位线分别在触发器43的输入/输出控制部分4处连接到触发器43的设置和复位输入。然后，每当IOC置位和复位指令出现时，触发器43的输出被改变，并且然后提供给数据选择器42.因此，选择器43选择直接从输入部分6和输出部分7给出的外部输入/输出数据或从输入/输出图像存储器41给出的数据，并将其发送到部分3 。

9. 发明专利

JPS62109767A PACKER 失效
公开(公告)号：JPS62109767A
公开(公告)日：1987-05-20
申请号：JP24887685
申请日：1985-11-08
申请人： HITACHI LTD , HITACHI KEIYO ENG
发明人： AOKI TAKASHI , KOZUKA MICHIAKI , OSHIGA TAKAYUKI , FUJIWARA KATSUHIRO , KASAHARA TOSHIRO
IPC分类号： B65D61/00

10. 发明专利

JPS62107318A INTERNAL CIRCUIT STRUCTURE FOR LSI 失效
公开(公告)号：JPS62107318A
公开(公告)日：1987-05-18
申请号：JP24700385
申请日：1985-11-06
申请人： HITACHI LTD
发明人： KIMURA HIROYUKI , KASAHARA TOSHIRO , OSHIGA TAKAYUKI , FUJIWARA KATSUHIRO
IPC分类号： G06F3/00 , G06F5/06 , G06F5/16
摘要： PURPOSE:To reduce the capacity without lowering the function, by using one register in common by plural inputs and outputs. CONSTITUTION:A register 4 is a common register of input/output buffers 2, 3, and in which input/output buffer a data is stored is determined by a data selector 5. In this way, the number of gates can be curtailed by 5-10 gates per 1 bit. Also, a through-path which does not pass through the register 4 is provided, and a selector 6 is provided on the post-stage of the register (not shown in the figure), by which even against that which requires a simultaneity of 16 bits in an external equipment of a 16-bit access of an input/output buffer side, read-out and write can be executed by an access timing of a CPU itself.

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