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1. 发明专利

JPH0822994A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0822994A
公开(公告)日：1996-01-23
申请号：JP15557894
申请日：1994-07-07
申请人： HITACHI LTD
发明人： NANBA MITSUO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/732
摘要： PURPOSE:To realize fine structure of a bipolar transistor constituting a semiconductor integrated circuit device. CONSTITUTION:In a bipolar transistor wherein a base region 3, an emitter region 4 and a collector leading-out region 2 are formed on a semiconductor substrate, a base connection part 3a for leading out a base electrode is formed in the base region 3, an emitter connection part 4b for leading out an emitter electrode is formed in the emitter region 4, and a collector connection part for leading out a collector electrode is formed in the collector leading-out region 2, the base connection part 3a and the collector leading-out region 2 are arranged on the same straight line.

2. 发明专利

JPH05166825A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05166825A
公开(公告)日：1993-07-02
申请号：JP33326391
申请日：1991-12-17
申请人： HITACHI LTD
发明人： NANBA MITSUO , MORI HIROSHI , ISHIKAWA MICHIO , WAKIMOTO EIJI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/732
摘要： PURPOSE:To prevent the deterioration of an emitter/base junction so as to improve the reliability by setting the impurity concentration in the region above the depth of an emitter junction higher than that in the region within the emitter junction forming depth from the surface of a semiconductor. CONSTITUTION:The peak value of the concentration in a first base layer 2 is in the region within the emitter junction forming depth from the surface of a semiconductor, and the peak value of the concentration in a second base layer 2 is in the region above the emitter junction forming depth. And, the concentration of the impurities in the region above the emitter junction forming depth is higher than that in the region within the emitter junction forming depth. Accordingly, the intensity of an electric field can be reduced by the improvement of a base profile. Hereby, the generation of hot carriers is suppressed, and the life of a device improves sharply. What is more, the application of the stress voltage higher than before becomes possible, and the improvement of the speed of a circuit becomes possible.

3. 发明专利

JPH053204A SEMICONDUCTOR DEVICE RESISTANT TO ALPHA-RAY, INTEGRATED CIRCUIT, AND LOGIC CALCULATION DEVICE 失效
公开(公告)号：JPH053204A
公开(公告)日：1993-01-08
申请号：JP15436691
申请日：1991-06-26
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NAKAMURA TORU , ONOUCHI YUKIHIRO , SHIBA TAKEO , TAMAOKI YOICHI , NANBA MITSUO , WASHIO KATSUYOSHI , SHIMAMOTO HIROMI , TANABE MASAMICHI , HONMA NORIYUKI
IPC分类号： H01L27/06 , H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/082 , H01L29/73 , H01L29/732
摘要： PURPOSE:To provide a transistor structure capable of ultrahigh speed operation while preventing malfunctions such as soft errors so as to improve the reliability of ULSIs and large computers. CONSTITUTION:A transistor composed of a first region (101), a second region (102), and a third region (103) has at least one silicon part including an intrinsic region. The silicon part is bent in a plane or cross section. Therefore, the transistor having the bent structure is irradiated only at a small part with alpha-rays that tend to advance straight. The charge produced by a-ray irradiation is smaller as compared with the transistor's capacitance, and thus it is possible to prevent malfunction and realize ultrahigh speed operation.

4. 发明专利

JPH03211276A VACUUM TREATING DEVICE 失效
公开(公告)号：JPH03211276A
公开(公告)日：1991-09-17
申请号：JP611290
申请日：1990-01-17
申请人： HITACHI LTD
发明人： NANBA MITSUO , EZAKI SHINOBU
IPC分类号： C23C14/54 , C23C14/56
摘要： PURPOSE:To continuously treat a work in a vacuum state by providing a means for detecting a slit-shapes sealing spacing, etc., and utilizing the attraction force of an electromagnet by the signal from this means, by which the slit spacing can be adjusted. CONSTITUTION:This vacuum treating device is disposed with prevacuum chambers 2, 3 on the front and rear sides of a vacuum treating chamber 1. The treating device is sealed continuously from the outside by a sealing device 13 at the time when the work F is transported. The means 6 for detecting the film thickness of the work is provided on the feed side and the thickness of the work F is detected. A control means is operated by the detection signal thereof and the spacing of the above-mentioned sealing device 13 is adjusted by the attraction force of the electromagnet 15. A position detecting means 14 which detects the spacing of this sealing device is provided and the spacing is so controlled that always the prescribed seal spacing is attained.

5. 发明专利

JPS62195173A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62195173A
公开(公告)日：1987-08-27
申请号：JP3524186
申请日：1986-02-21
申请人： HITACHI LTD
发明人： SHIBA TAKEO , NANBA MITSUO , NAKAMURA TORU , NAKAZATO KAZUO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
摘要： PURPOSE:To reduce the ratio of the transit time of carriers in graft base regions to the total transit time of carriers in an SICOS type bipolar transistor by a method wherein inclinations spreading toward the depth direction are provided on the side walls of a single crystal semiconductor layer which is contacted with nonactive base regions. CONSTITUTION:After an n type buried layer 4 is formed in a p-type Si substrate, 1 an n-type Si epitaxial layer 3 and, selectively, Si oxide films 5 are formed. The layer 3 is etched with the oxide films 5 as masks to form isolation trenches 2. At that time, inclinations spreading toward the depth direction are provided on the side walls 30 of the layer 3. After Si oxide films 8 are formed on the parts of the side walls 30 of the layer 3 and Si oxide films 6 are formed in the isolation trenches 2, a polycrystalline Si layer 7 is deposited over the whole surface. After the layer 7 is doped with a p-type impurity, the layer 7 is removed by etching except nonactive base regions 9. After that a hot oxide film 10 is formed. Then a p-type impurity is diffused into the layer 3 by hot diffusion to form graft base regions 11. Then a p-type active base region 12, an n-type emitter region 14, an n-type collector region 13 and electrodes 15 are formed.

6. 发明专利

JPS60154681A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS60154681A
公开(公告)日：1985-08-14
申请号：JP1007284
申请日：1984-01-25
申请人： HITACHI LTD
发明人： MIZUO SHIYOUICHI , NANBA MITSUO , SAIDA HIROJI , SUGASHIRO SHIYOUJIROU
IPC分类号： H01L21/8229 , H01L27/10 , H01L27/102 , H01L29/47 , H01L29/872
摘要： PURPOSE:To reduce the series resistance of a Schottky diode (SBD) and to suppress the irregular resistance by employing a structure that the density increases from the surface to an N type buried layr for the SBD of an LSI. CONSTITUTION:In the drawing of the density distribution of depthwise direction of the SBD, 9 is the density distribution of the SBD diffused layer of the case that P is implanted by the conventional method, and 10 is that of the case that formed by this method. A low density layer is not formed between a SBD diffused layer 10 and an N type buried layer 6, and the resistance may be suppressed to low value. The density gradient of the layer 10 at the connecting portion of the layer 10 with the layer 6 is mostly eliminated and reduced. Thus, the variation in the resistance due to the variation in the thickness of an epitaxially grown film can be suppressed to small value. The layers 9, 10 have the same surface density, and the same forward voltage VF is applied, but the quantity of implanting phsophorus per unit area of the case of the layer 10 is increased. Since the surface density of the SBD diffused layer is suppressed to low value as compared with the maximum density of the diffused layer, ion implanted amount can be increased with respect to the constant VF, thereby reducing the series resistance of the SBD.

7. 发明专利

JPS6080274A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6080274A
公开(公告)日：1985-05-08
申请号：JP18687483
申请日：1983-10-07
申请人： HITACHI LTD
发明人： NANBA MITSUO , KAWAMOTO YOSHIFUMI , MIZUO SHIYOUICHI
IPC分类号： H01L21/8222 , H01L21/331 , H01L27/06 , H01L29/72 , H01L29/73 , H01L29/732
摘要： PURPOSE:To contrive to improve the emitter-base widthstand voltage by a method wherein intrinsic base region and an external base region joined to its rim are formed in the surface layer of a semiconductor substrate, and an emitter region is provided in the former base region; when lead-out parts are installed to the emitter region and the latter base region, respectively, the external base lead-out part is insulated from the emitter lead-out part by means of an insulation film of the same thickness as that of the former lead-out part. CONSTITUTION:The intrinsic P type base region 2 and the shallow P type external base region 3, a contact region joining to its rim, are formed in the surface layer of the N type Si substrate 11 serving as the collector, and the N type emitter region 5 is provided in the region 2. Next, the emitter lead-out part 6 is installed to the region 5, and the base lead-out part 4 to the region 3. At this time, an insulation film 7 of the same thickness as that of the part 4 is interposed between the regions 2 and 3 on the surface, and the outer periphery of the part 4 is provided with a field insulation film 11. Thus, the region 3 is made shallow, and the part 4 is adhered over the entire surface thereof.

8. 发明专利

JPS59207659A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS59207659A
公开(公告)日：1984-11-24
申请号：JP8088283
申请日：1983-05-11
申请人： Hitachi Ltd
发明人： NANBA MITSUO , SAIDA HIROJI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72
CPC分类号： H01L29/72
摘要： PURPOSE:To reduce base resistance, by using an insulating film as a mask with respect to the introduction of emitter impurities, so that the film does not work as a mask for the ion implantation into a base, and thickly growing a polysilicon insulating film thicker than the insulating film. CONSTITUTION:An SiO2 film 2 is formed on an Si substrate 1. An Si3N4 film 3 is attached to the film 2. Then heat treatment is performed in an oxidizing atmosphere. A part of the Si3N4 film 3 is oxidized and an SiO2 film 4 is formed. Then, polycrystal Si 6 is formed. As ions are implanted in the polycrystal Si 6, annealing treatment is performed, and an emitter layer 8 is formed. Thereafter, with B as a source, an intrinsic base layer 9a and an outer base layer 9b are formed by base ion implantation. B ions are activated by the annealing of an N2 atmosphere.
摘要翻译：目的：为了降低基极电阻，通过使用绝缘膜作为掩模来引入发射极杂质，使得该膜不能作为离子注入基底的掩模，并且厚度增长多晶硅绝缘膜较厚绝缘膜。构成：在Si衬底1上形成SiO 2膜2.将Si 3 N 4膜3附着在膜2上。然后在氧化气氛中进行热处理。一部分Si 3 N 4膜3被氧化并形成SiO 2膜4。然后，形成多晶Si 6。当离子注入到多晶Si 6中时，进行退火处理，形成发射极层8。此后，以B +作为源，通过基底离子注入形成本征基极层9a和外部基极层9b。 B离子通过N2气氛退火而被激活。

9. 发明专利

JPS59161835A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS59161835A
公开(公告)日：1984-09-12
申请号：JP3582083
申请日：1983-03-07
申请人： Hitachi Ltd
发明人： NANBA MITSUO , NAKAMURA TOORU , MIZUO SHIYOUICHI
IPC分类号： H01L21/027 , H01L21/20 , H01L21/74
CPC分类号： H01L21/74
摘要： PURPOSE:To obtain the buried layer without having increased resistance while the number of mask layer is being reduced by a method wherein an insulating film is provided in advance on a buried layer formed region of shallow junction depth, the region other than the buried layer forming region is oxidized using said insulating film as a mask, the mask is removed, and a buried layer is formed thereon. CONSTITUTION:An SiO2 film 22 and an Si3N4 film 23 are laminated and coated on an Si substrate 21, these films located on the region other than the regions E and F are removed by performing a photo etching and a dry etching, and thick SiO2 films 24 to be connected to the film 22 located under the film 23 are formed on the exposed surface of the substrate 21 by performing a heat treatment. Then, the film 23 is removed together with the film 22 located below it, a thick SiO2 film 24 is left on the region other than the regions E and F located on the surface of the substrate 21, and buried layers 25E and 25F are removed by diffusion in the substrate 21 located between the films 24. Subsequently, the unnecessitated film 24 is removed, a stepping 26 to be used for desired photo etching is generated between the surface of the substrate 21 and the surface of the layer 25E, an epitaxial layer 27 is grown on the whole surface, and a stepping 28 to be used for marker region corresponding to a stepping 26 is generated on the surface of said layer 27.
摘要翻译：目的：通过预先在浅层深度的埋层形成区域上预先设置绝缘膜的方法来减少掩模层的数量而不增加电阻而获得掩埋层，除了埋层形成之外的区域使用所述绝缘膜作为掩模氧化区域，去除掩模，并在其上形成掩埋层。构成：将SiO 2膜22和Si 3 N 4膜23层叠并涂覆在Si基板21上，通过进行光蚀刻和干法蚀刻除去位于区域E和F以外的区域的这些膜，并且厚SiO 2膜通过进行热处理，在基板21的露出面上形成连接到位于薄膜23下方的薄膜22的图24。然后，与位于其下方的膜22一起除去膜23，在位于基板21的表面上的区域E和F以外的区域上留下厚的SiO 2膜24，并且去除掩埋层25E和25F 通过在位于膜24之间的衬底21中扩散。随后，去除不需要的膜24，在衬底21的表面和层25E的表面之间产生用于期望的光刻蚀的步进26，外延层27在整个表面上生长，并且在所述层27的表面上产生用于与踏板26对应的标记区域的台阶28。

10. 发明专利

JPS5917281A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS5917281A
公开(公告)日：1984-01-28
申请号：JP12569582
申请日：1982-07-21
申请人： Hitachi Ltd
发明人： NANBA MITSUO
IPC分类号： H01L29/73 , H01L21/265 , H01L21/331 , H01L29/72
CPC分类号： H01L29/72
摘要： PURPOSE:To enable to finish the device whose junction depth of a high concentration graft base has not so much difference as compared with junction depth of an intrinsic base, and to prevent the device from increase of junction capacitance between the base and a collector, etc., by a method wherein a mask is selected as to act as the mask to ion implantation when an emitter layer is to be formed, but as not to act as the mask against ion implantation when the base layer is to be formed. CONSTITUTION:An SiO2 film 2 is formed on an Si substrate 1, and after on Si3N4 film 3 is formed thereon, the Si3N4 film 3 at the emitter forming region 4 is etched to be removed using dry etching technique. Ion implantation is performed in succession under the condition that the accelerating voltage is 30keV, the dose is 5X10 cm using As as the source, and an annealing treatment is applied at 950 deg.C for 20min to activate As ions 5. Then ion implantation is performed under the condition that the accelerating voltage is 25keV, the dose is 1X10 cm using B as the source in the condition of the same mask structure to form base junctions 6, 7. After then an annealing treatment is performed at 900 deg.C for 10min.
摘要翻译：目的：为了完成高浓度移植物基底的结深与本征基底的结深度不同的器件，并防止器件增加基极和集电极之间的结电容等。通过选择掩模作为当要形成发射极层时作为离子注入的掩模的方法，但是当要形成基底层时，作为不作为防止离子注入的掩模的方法。构成：在Si衬底1上形成SiO 2膜2，在其上形成Si 3 N 4膜3之后，使用干蚀刻技术蚀刻发射体形成区域4处的Si 3 N 4膜3。使用As +作为源，在加速电压为30keV，剂量为5×10 15 cm -2的条件下连续进行离子注入，并在950℃下进行退火处理20分钟激活As离子5.然后，在相同的掩模结构的条件下，使用B +作为源，在加速电压为25keV，剂量为1×10 14 cm -2的条件下进行离子注入形成基底结6,7。然后在900℃进行退火处理10分钟。

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