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    • 5. 发明专利
    • DE60323969D1
    • 2008-11-20
    • DE60323969
    • 2003-08-28
    • HITACHI LTD
    • NAKAMURA SHUJISHIMADA KENTARO
    • G06F11/20G06F12/08G06F3/06G06F12/16
    • The present invention provides a storage system capable of having a large-scale configuration for maintaining a write access response speed and reliability upon an occurrence of a failed cache and its control method. Plural clusters that control a disk drive connected thereto and have a cache memory are connected to one another through a cross coupling network, and write data in the cache memory of the clusters is mutually made redundant in the cache memories in two clusters that jointly use the same disk drive. When a failure occurs in the cache memory, the cluster that uses the disk drive jointly with the cluster having the cache memory in which the failure occurs performs processing for getting access to the disk drive operated by the cluster having the cache memory in which the failure occurs, and the other normally-operated cluster is operated to only make redundant the write data in the cache memory in its cluster.
    • 10. 发明专利
    • DE60230101D1
    • 2009-01-15
    • DE60230101
    • 2002-02-15
    • HITACHI LTD
    • YOSHIDA AKIRANAKAMURA SHUJI
    • G06F3/06G06F12/08G06F12/00G06F13/00G06F13/12
    • Disk array system is presented wherein the plurality of disk array controlling units operate as the sole disk array controller so as to restrain the performance of the cache memory sections of the respective disk array controlling units from deteriorating owing to their physical packaging locations and to maximize the performance thereof in proportion to the number of the controlling units in use. Disk array controller is provided, which controller comprises a host switch interface section, the plurality of respective disk array controlling units provided with a channel interface section, a disc interface section and a cache memory section and a mutual connection network in connection with the channel interface sections, the disc interface sections and the cache memory sections of said respective disk array controlling units. Access performance to the cache memory sections that are dispersedly disposed between the respective disk array controlling units improves so as to enhance the performance of the disk array controller in proportion to the number of the disk array controlling units in use.