专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2003133557A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003133557A
公开(公告)日：2003-05-09
申请号：JP2001329620
申请日：2001-10-26
申请人： HITACHI LTD
发明人： SHIRAI NOBUYUKI , MATSUURA NOBUYOSHI , NAKAZAWA YOSHITO
IPC分类号： H01L29/872 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L27/095 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/40 , H01L29/45 , H01L29/47 , H01L29/78 , H01L31/0336 , H01L31/062
摘要： PROBLEM TO BE SOLVED: To miniaturize a semiconductor device containing power transistors and SBD (Schottky barrier diode) elements. SOLUTION: This semiconductor device is constituted as follows: The main surface of a semiconductor substrate has first and second regions. A plurality of first and second conductors are formed on each of the first and second regions. A first semiconductor region, and a second semiconductor region located in the first semiconductor region and having an opposite conductivity type to that of the first semiconductor region, are formed between adjacent first conductors in the first region. A third semiconductor region having the same conductivity type as that of the second semiconductor region and having a lower impurity concentration than that of the second semiconductor region is formed between adjacent second conductors in the second region. Metal is formed on the second region of the semiconductor substrate. The third semiconductor region has a metal contact that is connected to the metal, while the metal is electrically connected to the second semiconductor region. The distance between centers of the adjacent first conductors in the first region is shorter than that between centers of the adjacent second conductors in the second region.

2. 发明专利

JP2003017697A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2003017697A
公开(公告)日：2003-01-17
申请号：JP2001201804
申请日：2001-07-03
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MATSUURA NOBUYOSHI , MIYAGUCHI YASUYUKI , HAYASHI HATSUO , KOYANO MASAFUMI
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L27/04 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/4238 , H01L29/7811 , H01L2224/0603 , H01L2224/48091 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To reduce the ON resistance and switching loss of a vertical MOSFET. SOLUTION: A semiconductor device is provided with a semiconductor substrate, a plurality of vertical field effect transistor cells formed in a parallelly connected state on the semiconductor substrate, a gate potential power feed part provided on the surface of the semiconductor substrate, first gate wiring provided on the semiconductor substrate and electrically connected to the gate potential power feed part, and second gate wiring provided on the semiconductor substrate electrically connected to the first gate wiring and also connected to the gate electrodes of the respective transistor cells. The second gate wiring is extended from the first gate wiring and is provided with a tip. Also, the adjacently extended ones of the second gate wiring are extended from the first gate wiring so as to turn a current flowing direction to mutually opposite directions.
摘要翻译：要解决的问题：降低垂直MOSFET的导通电阻和开关损耗。解决方案：半导体器件设置有半导体衬底，在半导体衬底上以并联连接状态形成的多个垂直场效应晶体管单元，设置在半导体衬底的表面上的栅极电力馈电部分，第一栅极布线并且电连接到栅极电力馈送部分，以及设置在半导体衬底上的电连接到第一栅极布线并且还连接到各个晶体管单元的栅电极的第二栅极布线。第二栅极布线从第一栅极布线延伸并且设置有尖端。此外，第二栅极布线的相邻延伸的第一栅极布线从第一栅极布线延伸，以将电流流动方向转向相互相反的方向。

3. 发明专利

JPH11233755A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH11233755A
公开(公告)日：1999-08-27
申请号：JP2950598
申请日：1998-02-12
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： TAKAYANAGI YUJI , MATSUURA NOBUYOSHI , NEMOTO TOYOICHI , TAKAHASHI KAZUYUKI
IPC分类号： H01L29/744 , H01L29/74
摘要： PROBLEM TO BE SOLVED: To provide a thin semiconductor device by forming the gate electrode of a GTO (gate turn-off thyristor) in a multiple structure. SOLUTION: In a GTO, a multiple electrode 108 consisting of a four-layer metal of an aluminum layer 101, a titanium layer 102, a nickel layer 103, and a metal layer 104 is formed at a part where a P base layer 202 is exposed to a semiconductor substrate surface, and a gate lead 13 is connected to the surface of the multiple electrode 108 via solder 105. As a result, by directly gluing a gate pad, the need for a conventional gate pressurization mechanism is eliminated, thus making thin the GTO element.

4. 发明专利

JPH1041498A GATE TURN-OFF THYRISTOR STACK 失效
公开(公告)号：JPH1041498A
公开(公告)日：1998-02-13
申请号：JP19307296
申请日：1996-07-23
申请人： HITACHI LTD
发明人： WAKIZAWA YUUJI , MATSUURA NOBUYOSHI
IPC分类号： H01L29/74 , H01L29/744
摘要： PROBLEM TO BE SOLVED: To make the best use of the performance of a GTO thyristor preventing a current from concentrating on its region where more stress is induced when an unbalanced load is applied to the GTO thyristor by a method wherein the first region of a unit device is set smaller in current density than the second region when the unit device is equal in ON-state voltage. SOLUTION: A water-cooled fin 1 is equipped with an electrode lead-out terminal in one piece. The water-cooled fin is inserted between a diode 2 of small electrode diameter and a gate turn-off thyristor (GTO) 3 with electrodes larger in diameter than those of the diode 2. The GTO thyristor 3 is formed of a semiconductor pellet composed of a region A of the same diameter with the diode 2 and an outer region B, wherein the region A is smaller in current density than the region B when the GTO thyristor 3 is uniformly pressurized in an ON-state. The GTO thyristor is so formed as to make the region A shorter in a turn-off time than the region B. By this setup, a GTO thyristor stack can be enhanced in controllable current and lessened in size and cost.

5. 发明专利

JPH08204169A GTO THYRISTOR AND ITS MANUFACTURE 失效
公开(公告)号：JPH08204169A
公开(公告)日：1996-08-09
申请号：JP693495
申请日：1995-01-20
申请人： HITACHI LTD
发明人： MATSUURA NOBUYOSHI , SUGAWARA YOSHITAKA , ONOSE HIDEKATSU
IPC分类号： H01L29/74 , H01L21/332
摘要： PURPOSE: To obtain high cut-off capability, by forming parallel recessed parts in the bottom of a second stage trench formed from an N-emitter layer to an R-base layer of a gate turn-off thyristor, and forming heavily doped R layers on the surface of the R-base layer, along the second stage trench. CONSTITUTION: An N-emitter layer layer 5, an R-base layer 6, an N-base layer 7 and an R-emitter layer 8 are continuously formed between the main surfaces 11 and 12 of a semiconductor substratum 1 composed of silicon. The one main surface 11 is constituted as an uneven surface. On its protruding part, the strip type N-emitter layer 5 is exposed. On the recessed part, the R-base layer 6 is exposed. The R-emitter layer 8 is exposed on the other main surface 12, alternately with N regions 9. A cathode electrode 2, an anode electrode 3 and a gate electrode 4 are formed by an Al evaporation method. Two-stage trenches are formed from the emitter layer 5 to the R-base layer 6. Heavily doped R layers 10 are formed along the second trenches. Thereby cut-off capability can be improved without deteriorating the breakdown voltage between the cathode and the gate.

6. 发明专利

JP2002217416A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002217416A
公开(公告)日：2002-08-02
申请号：JP2001007191
申请日：2001-01-16
申请人： HITACHI LTD
发明人： TAKAGAWA KYOICHI , SAKAMOTO MITSUZO , MATSUURA NOBUYOSHI , KOYANO MASAFUMI
IPC分类号： G06F1/26 , H01L23/495 , H01L25/07 , H01L25/18 , H01L27/04 , H01L27/088 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To improve a power supply circuit in power supply efficiency. SOLUTION: A power MOS FET Q1, as the high side of a composite power MOS-FET PM which constitutes a DC-DC converter, is composed of a lateral MOS-FET, and a power MOS-FET Q2 as the low side of the composite power MOS-FET PM is composed of a vertical MOS-FET.

7. 发明专利

JP2001024193A TRENCH GATE SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2001024193A
公开(公告)日：2001-01-26
申请号：JP19853199
申请日：1999-07-13
申请人： HITACHI LTD
发明人： MATSUURA NOBUYOSHI , YANOKURA EIJI , MIYAGUCHI YASUYUKI , HAYASHI HATSUO
IPC分类号： H01L21/336 , H01L29/40 , H01L29/423 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To prevent concentration of electric fields on the bottom of a gate lead-out trench in a peripheral area by protruding a second groove into an epitaxial layer through a well layer, and by making the protruding distance of the groove into the epitaxial layer shorter than the protruding distance of a first groove into the epitaxial layer. SOLUTION: An epitaxial layer 2 is formed on the first main surface of a silicon substrate 1 and an annular p-well layer 4 is formed in the inner peripheral area GR of a field oxide film 3 on the surface of the epitaxial layer 2. The p-well layer 4 is made shallower than a p-channel layer 8 and a peripheral trench 5b is made shallower than the trench 5A of an MOS section and deeper than the p-well layer 4. The projecting distance of the peripheral trench 5B into the epitaxial layer 2 is made shorter than that of the trench 5A into the epitaxial layer 2.

8. 发明专利

JPH10107051A PRESSURE-WELDING TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10107051A
公开(公告)日：1998-04-24
申请号：JP25581096
申请日：1996-09-27
申请人： HITACHI LTD
发明人： SAITO KATSUAKI , MATSUURA NOBUYOSHI
IPC分类号： H01L29/74 , H01L21/52
摘要： PROBLEM TO BE SOLVED: To prevent the generation of the unevenness of pressing stresses from pressing electrodes by a method wherein the pressing electrodes are respectively provided with two regions or more, the first regions of the regions are formed as the vicinities of the outlines of the shapes of the electrodes coming into contact with electrode films, the second regions and succeeding regions are formed as the regions other than the first regions and the yield stresses of the first regions are set larger than those of the second regions and succeeding regions. SOLUTION: A semiconductor substrate comes into contact thermally and electrically with buffer electrode plates 116 and 117. The plates 116 and 117 are pressed by pressing units and the like, which are provided on the outside of a semiconductor element, through pressing electrodes 118 and 119 and 21 reduction in the contact resistance between the electrode plates 116 and 117 is contrived. The electrodes 118 and 119 in this case consist of two materials, the first materials 125 respectively form the vicinities of the shapes of the outlines of the electrodes 118 and 119 and the second materials 126 respectively form sites other than the vicinities of the shapes of the outlines of the electrodes 118 and 119. The yield stress of the materials 125 is about 1.2 times larger than the yield stress of the materials 126. By applying an even pressing force to the thyristor, an even heat dissipation within the surfaces of the substrate and the even electrical contact within the surfaces of the substrate can be contrived and a reduction in pressing stresses from the electrodes 118 and 119 that a semiconductor device results in being broken due to an insufficient pressing to the substrate can be prevented.

9. 发明专利

JPH07193218A INJECTION OF CHARGED PARTICLES AND SEMICONDUCTOR DEVICE HAVING CRYSTAL DEFECT LAYER 失效
公开(公告)号：JPH07193218A
公开(公告)日：1995-07-28
申请号：JP33294493
申请日：1993-12-27
申请人： HITACHI LTD
发明人： MATSUURA NOBUYOSHI , ONOSE HIDEKATSU , TAKAYANAGI YUJI
IPC分类号： H01L29/74 , H01L21/265 , H01L21/322 , H01L29/68 , H01L29/744
摘要： PURPOSE:To provide a GTO thyristor which has no increase in on-state voltage or leakage current when charged particles are injected in an n-base layer and then a crystal defect layer 9 is formed. CONSTITUTION:A GTO thyristor which consists of an n base layer 1, a p base layer 2 joined to one face of the n base layer 1, an n emitter layer 3 joined to a part of the p base layer 2, and a plurality of p emitter layers 4 and a plurality of n layers 5 which are thicker than the p emitter layers 4. The p emitter layers 4 and the n-I-layers 5 are joined alternately to the other face of the n base layer 1. In the n base layer 1, a crystal defect layer 9 is formed by injecting charged particles. In such a GTO thyristor, the crystal defect layer 9 is formed only in a part of the n base layer 1 which is in the thickness of 20mum or above from the p emitter layers 4. The crystal defect layer 9 is so formed that a crystal defect concentration profice in the crystal defect layer 9 may be sloping in one direction (aslant) according to the depth from the surface of the p emitter layers 4.

10. 发明专利

JP2004213144A Method, device and program for supporting design of power converter semiconductor device, recording medium of design support program and powder converter semiconductor device developing system 有权
公开(公告)号：JP2004213144A
公开(公告)日：2004-07-29
申请号：JP2002379215
申请日：2002-12-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： IWASAKI TAKAYUKI , MORI MUTSUHIRO , SHIRAISHI MASAKI , MATSUURA NOBUYOSHI
IPC分类号： G06F17/50 , H01L21/02 , H02M1/00
摘要： PROBLEM TO BE SOLVED: To shorten developing time by consistently performing simulation from process specification to a power converter characteristic in development of a power converter semiconductor device.
SOLUTION: A characteristic of the power converter including at least two semiconductor devices constituting the power converter and constitution elements of a control system and a circuit system is simulated by using a finite element method in a process simulation part 13 on the semiconductor device and by approximating other elements by a formula model in a power converter simulation part 17. Thus, simulation from manufacture specification of the semiconductor device to the characteristic of the power converter can consistently be performed in a short time. Developing time of the power converter on a customer side can be shortened by using simulation in information exchange with a customer.
COPYRIGHT: (C)2004,JPO&NCIPI

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式