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1. 发明专利

JP2003258635A SEMICONDUCTOR INTEGRATED CIRCUIT HAVING ANALOG CIRCUIT, DIGITAL CIRCUIT AND TEST METHOD THEREFOR 审中-公开
公开(公告)号：JP2003258635A
公开(公告)日：2003-09-12
申请号：JP2002059015
申请日：2002-03-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAMEYAMA SADAFUMI , ISHIHARA YUKITO , KOJIMA KOJI , OKA MIKI
IPC分类号： G01R31/316 , H03M1/10
摘要： PROBLEM TO BE SOLVED: To provide a test technique capable of evaluating an analog circuit with high accuracy by use of an internal circuit in an analog-digital mixed semiconductor integrated circuit, having analog circuits including an digital-to- analog converter (DAC), an analog-to-digital converter (ADC), etc., and digital circuits including a digital control signal generator, a digital waveform generator, etc. SOLUTION: In a semiconductor integrated circuit having a PLL circuit, a digital synthesizer digital control signal generator, the DAC, and the ADC, which is configured so that the digital synthesizer digital control signal generator, the DAC and the ADC operate in synchronization with a signal generated in the PLL circuit, a current-to-voltage converter is provided between an output terminal of the DAC and an input terminal of the ADC, so that a DAC output can be input directly to the ADC, without through a filter. COPYRIGHT: (C)2003,JPO

2. 发明专利

JPH0652281A TIME SERIES DATA ANALYSIS SYSTEM 失效
公开(公告)号：JPH0652281A
公开(公告)日：1994-02-25
申请号：JP20760692
申请日：1992-08-04
申请人： HITACHI LTD , HITACHI KEIYO ENG , HITACHI INF & CONTROL SYST
发明人： NAKAYAMA HIDEO , NISHITANI TAKUJI , KOJIMA KOJI , NAKANO TOSHIHIKO
IPC分类号： G06T3/00 , G06T11/80 , G06F15/62 , G06F15/21 , G06F15/66
摘要： PURPOSE:To provide the interface for a user storing a sample to be used for analyzing the time series data. CONSTITUTION:An approximate polygonal line pattern generation section 101-1, when the user draws the polygonal line like tracing the time series data, generates the approximate polygonal line pattern based on it. A sample acquisition processing section 101-2 displays the time series data and the approximate polygonal line pattern and takes it as the sample when the user specifies the characteristic part of the fluctuation. A sample mixing processing section 101-3 generates a 'cross' sample mixing plural samples with the same name. A detection test processing section 101-4 detects parts similar to the sample from the approximate polygonal line pattern and displays the screen comparing the sample similarity part and the characteristic part specified by the user overlapped on it. A dictionary drawing processing section 101-5, when the user arbitrarily draws the shape representing the characteristic part of the fluctuation of the time series data, takes it as the sample. Thus, it is effective in monitoring the state of such as plants and detecting abnormality.

3. 发明专利

JPH064997A SIGNAL PROCESSING DEVICE AND MAGNETIC RECORDING DEVICE USING IT 失效
公开(公告)号：JPH064997A
公开(公告)日：1994-01-14
申请号：JP15914592
申请日：1992-06-18
申请人： HITACHI LTD
发明人： TANAKA SATOSHI , MATSUSHIGE HIROMI , KOJIMA KOJI , HANAMURA SHOJI
IPC分类号： G11B5/09 , G11B20/10
摘要： PURPOSE:To realize a data discriminating circuit which can correctly discriminate 1 or 0 even if amplitude of an input signal is greatly varied by providing an expected value renewal circuit in a signal processing device. CONSTITUTION:An expected value using for discriminating 1 or 0 is generated by an expected value renewal circuit which renews the expected value based on the peak value of sampling data. The expected value renewal circuit is constituted of an envelope value renewal circuit and the expected value calculating circuit. In order to renew the envelope value, an envelope value Venv stored in a register 3 is renewed based on an absolute value Vabs of data sampled by an A/D converter 2 with the same timing as a peak detecting signal from a peak detector 1. The envelope value is multiplied by a constant Adc in a multiplier 8 of an expected value calculating circuit and an expected value Ad is generated, and a second expected value Ap in which a constant Apdc is added to the expected value Ad is generated in an adder 9. Expected values Ad and Ap are discriminated and compared by discriminating circuits of two systems, when each value is different, a pointer signal is generated and an error is quickly detected.

4. 发明专利

JPH05252000A 失效
公开(公告)号：JPH05252000A
公开(公告)日：1993-09-28
申请号：JP4823892
申请日：1992-03-05
申请人： HITACHI LTD
发明人： KOJIMA KOJI , MIYASAKA HIDEKI , MATSUSHIGE HIROMI , OKADA YUTAKA , TANAKA SATOSHI , HANAMURA SHOJI
IPC分类号： H03H21/00 , H04B3/14
摘要： PURPOSE:To obtain an adaptive equalizer with a small circuit scale by using an infinite impulse response filter (IIR filter) having a low pass filter characteristic (cut-off frequency) of the same degree to that of a moving mean circuit. CONSTITUTION:A coefficient C of an adaptive filter comprising a finite impulse response filter (FIR filter) 8 is used for a control variable. A square mean value of an error e (=Y-a) between an output Y of the FIR filter 8 and a value (a) of an output expected value 3 is used for an evaluation quantity. The evaluation quantity is partially differentiated by using the coefficient C and the revision quantity of the coefficient C is obtained. In the case of calculating the coefficient revision quantity, an IIR filter 7 is used to obtain a mean value equivalently. When the IIR filter 7 is expressed by a transfer function, the transfer function has at least one pole. Then the circuit scale is reduced by selecting the coefficient to decide the cut-off frequency of the IIR filter 7 to be one over 2's power or at most the sum or the difference of them.

5. 发明专利

JPH05152935A CONTROL CIRCUIT AND INTEGRATED CIRCUIT CONTROLLED BY THE CONTROL CIRCUIT 失效
公开(公告)号：JPH05152935A
公开(公告)日：1993-06-18
申请号：JP5994791
申请日：1991-03-25
申请人： HITACHI LTD
发明人： NAKASE JUNKO , MATSUURA TATSUJI , KOJIMA KOJI , TANAKA SATOSHI
IPC分类号： H03K17/04 , G11C11/407 , G11C11/408 , H03K17/30 , H03K19/017 , H03K19/094
摘要： PURPOSE:To provide the control circuit which is operated for a desired propagation delay time tpd by setting a threshold voltage of an integrated circuit stably. CONSTITUTION:A ring oscillator 4 having an oscillating frequency (f) reflected with a propagation delay time tpd of a FET of a circuit 6 to be controlled whose component is the FET is provided and a voltage generating circuit 2 generates a control voltage Vb by the output of a comparator circuit 1 comparing a reference frequency fref and the frequency (f) and the voltage is added to a base electrode 6a of the control circuit 6 to be controlled. Thus, the dispersion in the propagation delay time tpd in the integrated circuit is suppressed and the yield is improved. The high speed operation of the circuit is realized by setting the propagation delay time tpd small when the integrated circuit is applied to an integrated circuit with a low threshold voltage.

6. 发明专利

JPH03102907A MODEL FREQUENCY CONVERTER 失效
公开(公告)号：JPH03102907A
公开(公告)日：1991-04-30
申请号：JP23998289
申请日：1989-09-18
申请人： HITACHI LTD
发明人： KOJIMA KOJI , UMAJI TORU , OKADA YUTAKA
IPC分类号： G09G5/36 , H03H17/00 , H03H17/06 , H03H21/00
摘要： PURPOSE:To obtain a model frequency converter excellent in the circuit utilizing efficiency and the general-purpose performance by using a multiplier in which the inputted coefficients, their order and procedure of multiplication are variable, an adder and applying product sum operation to desired transfer functions. CONSTITUTION:An input digital signal (model frequency f1) is inputted to a multiplier 6 through a register 204 and coefficient data from a coefficient memory 801 is inputted to the outer input terminal through a coefficient register (for frequency 3f1) 205. The result of multiplication is inputted to an adder 7 through a register (for frequency 3f1) 206. The output of the adder is stored respectively into addresses 0-3 of integration register ACC, REG 208 depending on desired transfer functions and inputted to the other terminal of the adder 7 through a register (for frequency 3f1) 207 as required. The content of the register 207 is set to zero by a multiplexer 402 in the machine cycle. AT the point of time of the end of operation by the adder 7 and the register 208, the output of the adder is stored in the register 209 in a prescriber timing. This is transferred to a register (for frequency f2) 210 to obtain an output of model frequency f2=4/5f1.

7. 发明专利

JPH01158814A HIGH SPEED SIGNAL PROCESSOR 失效
公开(公告)号：JPH01158814A
公开(公告)日：1989-06-21
申请号：JP31627587
申请日：1987-12-16
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： SUMI SHIGEO , UMAJI TORU , KOJIMA KOJI , OBA SHINYA
IPC分类号： H03H17/02 , G06F17/10
摘要： PURPOSE:To attain round-off without using any externally mounted adder by giving a high-order M-bit in N-bits of the result of product sum operation to an adder in the processor and using a data of the (M+1)th bit from the most significant bit as a carry input of the said adder. CONSTITUTION:A path from a register RB latching a filter output to an adder 2 is provided in a processor in which, e. g., 15 bits are used for the internal arithmetic processing and RB[14-7] being high-order 8 bits from the register RB are given to a register RD 1, from which they are given to an adder 2. Moreover, the bit RB[6] to be subject to round-off is given to a carry of the adder 2 receiving the RB[15-7] to truncate the low-order RB[5-0]. The 8-bit output subject to round-off is obtained as an output from an output register RO, then the round-off processing is attained without any externally mounted circuit and any excess increase in the program steps.

8. 发明专利

JPS6423366A HIGH-SPEED SIGNAL PROCESSOR 失效
公开(公告)号：JPS6423366A
公开(公告)日：1989-01-26
申请号：JP17899287
申请日：1987-07-20
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： UMAJI TORU , KOJIMA KOJI , SUMI SHIGEO , OBA SHINYA
IPC分类号： G06F17/10
摘要： PURPOSE:To shorten a delay time and to cut on access time down to

9. 发明专利

JP2001273729A DIGITAL DATA REPRODUCING DEVICE AND REPRODUCING METHOD 失效
公开(公告)号：JP2001273729A
公开(公告)日：2001-10-05
申请号：JP2000089106
申请日：2000-03-28
申请人： HITACHI LTD
发明人： HOSHISAWA HIROSHI , KOJIMA KOJI , NAGAI YUTAKA
IPC分类号： G06F11/10 , G06F12/16 , G11B20/18 , H03M13/05 , H03M13/33
摘要： PROBLEM TO BE SOLVED: To surely execute demodulation and error correction processing and to improve the reliability of reproduction data even if there are many errors and missing of part of the data in the digital data to be inputted. SOLUTION: The input data of ECC block constitution of iterated codes is demodulated in a demodulation circuit 7 and reliability flags indicating the detection condition of SYNC codes and IDs by each line of the ECC blocks and write flags of the values changing by each of the ECC blocks are added to the data. Such demodulated data is written to a RAM. When the writing of the one ECC block ends, this ECC block is read out and is supplied to an error correction circuit 11 and, first, the PI correction by each line is executed. At this time, the error position pointer P1 meeting the number of the detected errors and the error position pointer P2 meeting the reading out of the reliability flags and write flags are formed. Next, the PO correction of this ECC block is executed in the error correction circuit 11 and the error positions are determined according to the error position pointers P1 and P2 in disappearance correction.

10. 发明专利

JP2001222865A DIGITAL SIGNAL REPRODUCING DEVICE AND REPRODUCING METHOD 失效
公开(公告)号：JP2001222865A
公开(公告)日：2001-08-17
申请号：JP2000032726
申请日：2000-02-04
申请人： HITACHI LTD
发明人： IKEDA MASAKAZU , KOJIMA KOJI , NAGAI YUTAKA , HOSHISAWA HIROSHI
IPC分类号： G11B20/10 , G11B20/18
摘要： PROBLEM TO BE SOLVED: To reduce the number of times of access to a temporary storage means when reproducing a disk having large capacity at high speed. SOLUTION: Data obtained by demodulating data read out from a disk is not recorded once in a storage means, but recorded in a temporary storage means after error correction in a row direction is performed. Next, error correction in a column direction is performed for data recorded in the temporary storage means, scramble processing is performed at the same time when data of which the error is already corrected and which is recorded in the temporary storage means is outputted. Thereby, the access to the temporary storage means is constituted of three times of access of write-in processing of row direction data, error correction processing in a column direction, and output processing in a row direction by processing simultaneously conforming to features of data operation, thereby, accessing times to the temporary storage means can be reduced.

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