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1. 发明专利

DE68928376D1 未知
公开(公告)号：DE68928376D1
公开(公告)日：1997-11-13
申请号：DE68928376
申请日：1989-11-02
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： NARITA MASAHISA , KAZIWARA HISASHI , ASAI TAKESHI , MORINAGA SHIGEKI , KIDA HIROYUKI , WATABE MITSURU , NAKAMIKAWA TETSUAKI , KAWASAKI SHUNPEI , TATEZAKI JUNICHI , NAKAGAWA NORIO , KASHIWAGI YUGO
IPC分类号： G06F7/52 , G06F7/483 , G06F7/535 , G06F7/552 , G06F7/57
摘要： An appts for multiplication, division and extraction of the square root which determines the value of a function of multiplication, division or extraction of the square root by iterated approximation. A multiplier, adder/subtractor and shifter each has a predetermined bit width and connected to a bus. The output of the multiplier is inputted to the adder/subtractor or to the shifter and the result is again inputted to the multiplier through the bus. This operation is repeated. A shifter and a calculator connected to a second bus through a switch have a bit width greater than the predetermined bit width, are used for large-scale calculation and prevent a drop in calculation speed.

2. 发明专利

DE68928376T2 未知
公开(公告)号：DE68928376T2
公开(公告)日：1998-04-02
申请号：DE68928376
申请日：1989-11-02
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： NARITA MASAHISA , KAZIWARA HISASHI , ASAI TAKESHI , MORINAGA SHIGEKI , KIDA HIROYUKI , WATABE MITSURU , NAKAMIKAWA TETSUAKI , KAWASAKI SHUNPEI , TATEZAKI JUNICHI , NAKAGAWA NORIO , KASHIWAGI YUGO
IPC分类号： G06F7/52 , G06F7/483 , G06F7/535 , G06F7/552 , G06F7/57
摘要： An appts for multiplication, division and extraction of the square root which determines the value of a function of multiplication, division or extraction of the square root by iterated approximation. A multiplier, adder/subtractor and shifter each has a predetermined bit width and connected to a bus. The output of the multiplier is inputted to the adder/subtractor or to the shifter and the result is again inputted to the multiplier through the bus. This operation is repeated. A shifter and a calculator connected to a second bus through a switch have a bit width greater than the predetermined bit width, are used for large-scale calculation and prevent a drop in calculation speed.

3. 发明专利

GB2191317B A REGISTER ACCESS MECHANISM FOR A DATA PROCESSING SYSTEM 未知
公开(公告)号：GB2191317B
公开(公告)日：1990-05-16
申请号：GB8712079
申请日：1987-05-21
申请人： HITACHI LTD
发明人： NOJIRI TOHRU , KAWASAKI SHUNPEI , WATANABE TAN , SAKODA KOUSUKE
IPC分类号： G06F9/46 , G06F9/34 , G06F9/42 , G06F9/48 , G06F12/00 , G06F12/02
摘要： In order to divide a memory addressed unidimensionally into a plurality of memory areas and to manage these memory areas efficiently, the address to be accessed in the memory is determined on a software basis by a computer instruction by use of the value of a first pointer designating a memory area and the value of a second pointer designating the relative address in the designated memory area. The apparatus includes a memory (1) of 2 banks (2) each consisting of a 2 word memory area. An N-bit wide bank-designating pointer (3) and an N-bit wide offset- designating pointer (4) are combined in a pointer generating circuit (5) to give an access pointer (6).

4. 发明专利

GB2191317A Accessing memory 未知
公开(公告)号：GB2191317A
公开(公告)日：1987-12-09
申请号：GB8712079
申请日：1987-05-21
申请人： HITACHI LTD
发明人： NOJIRI TOHRU , KAWASAKI SHUNPEI , WATANABE TAN , SAKODA KOUSUKE
IPC分类号： G06F9/46 , G06F9/34 , G06F9/42 , G06F9/48 , G06F12/00 , G06F12/02 , G06F12/06
摘要： In order to divide a memory addressed unidimensionally into a plurality of memory areas and to manage these memory areas efficiently, the address to be accessed in the memory is determined on a software basis by a computer instruction by use of the value of a first pointer designating a memory area and the value of a second pointer designating the relative address in the designated memory area. The apparatus includes a memory (1) of 2 banks (2) each consisting of a 2 word memory area. An N-bit wide bank-designating pointer (3) and an N-bit wide offset- designating pointer (4) are combined in a pointer generating circuit (5) to give an access pointer (6).

5. 发明专利

JP2003330907A Microcomputer system 审中-公开
标题翻译：微型计算机系统
公开(公告)号：JP2003330907A
公开(公告)日：2003-11-21
申请号：JP2003113567
申请日：2003-04-18
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： MASUMURA SHIGEKI , NAKAMURA HIDEO , NOGUCHI YOSHIKI , KAWASAKI SHUNPEI , FUKADA KAORU , AKAO YASUSHI
IPC分类号： G06F15/78 , G06F13/38
摘要： PROBLEM TO BE SOLVED: To provide a bus operating method capable of easily changing a bus interface specification by increasing effective operation speeds of a bus, and a memory and peripheral function units connected to the bus, in a microcomputer system. SOLUTION: An access operation through buses 113 and 114 with bus masters 101 and 102 connected is executed in a pipeline manner, and control of the pipeline execution is carried out by an exclusive bus controller 111. An access delaying the pipeline operation is executed by buses 123 and 124 of a lower tier connected through a buffer means 112, and by a bus controller 121 exclusively used for the lower tier. Therefore, the bus band for access is improved, and bus interfaces having various specifications, and buses allowing parallel execution can easily be structured. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种总线操作方法，其能够通过在微计算机系统中增加总线的有效操作速度以及连接到总线的存储器和外围功能单元来容易地改变总线接口规范。解决方案：以流水线方式执行通过连接有总线主机101和102的总线113和114的访问操作，并且由专用总线控制器111执行流水线执行的控制。延迟流水线操作的访问是由通过缓冲装置112连接的下层的总线123和124执行，并且由专用于下层的总线控制器121执行。因此，改善了用于访问的总线频带，并且可以容易地构造具有各种规格的总线接口和允许并行执行的总线。版权所有（C）2004，JPO

6. 发明专利

JPH11102286A CIRCUIT AND METHOD FOR DIVISION 失效
公开(公告)号：JPH11102286A
公开(公告)日：1999-04-13
申请号：JP15814398
申请日：1998-06-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F7/537 , G06F7/52 , G06F7/535 , G06F9/30 , G06F9/305 , G06F9/32 , G06F9/38
摘要： PROBLEM TO BE SOLVED: To provide a circuit and a method for division with which a correct quotient can be easily found without detecting whether the partial remainder is '0' or not for each step of division for finding the quotient bit even when a dividend is negative. SOLUTION: When a dividend X is negative in the coded division expressed as Y (quotient) = X (dividend) ÷ 3 (divisor), for example, preprocessing is performed to define a value (X-1) subtracting '1' from the dividend X as a dividend. The preprocessing is processing for conceptionally shifting the coordinate axis of the quotient Y to left for '1'. The processing of division is performed in the shifting state. Thus, it is not necessary to discriminate whether the partial remainder is '0' or not conventionally every time in the middle of arithmetic processing and a hardware for that discrimination is unnecessitated as well. When finding the exact remainder, the found remainder is finally corrected.

7. 发明专利

JPH1196000A CPU AND MICROCOMPUTER 失效
公开(公告)号：JPH1196000A
公开(公告)日：1999-04-09
申请号：JP15814298
申请日：1998-06-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F9/30 , G06F9/35
摘要： PROBLEM TO BE SOLVED: To prevent the utilization of immediate data or the designation of an absolute address from being limited even when the number of bits of a fixed length instruction format is less than the data word length, by adopting the fixed length instruction format having bits less than the maximum data word length supplied to an instruction executing means. SOLUTION: IRH and IRL are the instruction buffers of 16 bits respectively, and an instruction is transferred through an internal data bus for the unit of 32 bits while being stored one by one. These instructions are loaded through a multiplexer MPX to an instruction register IR1. The instruction register IR1 has 16 bits. Thus, since the fixed length instruction format of 16 bits is adopted for the data word length of 32 bits, the judgement on where an instruction border exists, can be grasped before the completion of the preceding instruction, and the advantage of the simplification of instruction decode processing or the like is guaranteed. Further, the useless arrangement of bits is decreased and the utilization efficiency of a program memory is improved.

8. 发明专利

JPH06149731A MICROCOMPUTER SYSTEM 失效
公开(公告)号：JPH06149731A
公开(公告)日：1994-05-31
申请号：JP29677992
申请日：1992-11-06
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MASUMURA SHIGEKI , NAKAMURA HIDEO , NOGUCHI YOSHIKI , KAWASAKI SHUNPEI , FUKADA KAORU , AKAO YASUSHI
IPC分类号： G06F3/06 , G06F13/36 , G06F13/362
摘要： PURPOSE:To provide the operation system of a bus which can has its bus interface specifications easily changed by increasing the effective operation speeds of the bus, and a memory and a peripheral function unit connected to the bus in the microcomputer system. CONSTITUTION:Access operation through buses 113 and 114 to which bus masters 101 and 102 are connected is performed on a pipeline basis and the pipeline execution is controlled by a dedicated bus controller 111. Further, access which delays the pipeline operation is performed by buses 123 and 124 in a lower layer which are connected by a buffer means 112 and a bus controller 121 dedicated to the lower layer. The bus band of the access is improved and bus interfaces with various specifications and buses which enable parallel execution can easily be structured.

9. 发明专利

JP2001067219A CIRCUIT AND METHOD FOR DIVISION 失效
公开(公告)号：JP2001067219A
公开(公告)日：2001-03-16
申请号：JP2000212452
申请日：2000-07-13
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F7/537 , G06F7/52 , G06F7/535 , G06F9/30 , G06F9/34 , G06F9/355 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To prevent the use of immediate data and absolute address specification from being restricted even if the number of bits of a fixed-length instruction format is less than the length of a data word by adopting the fixed-length instruction format whose number of bits is less than maximum data word length. SOLUTION: A microcomputer has RISC type architecture and also has an instruction format of fixed length. A bus where data and instructions are transferred has 32-bit constitution. The instructions, on the other hand, are in 16-bit fixed-length instruction format. This 16-bit fixed-length instruction format is employed for 32-bit data word length and then where an instruction border is present can be decided before a last instruction is completed as well as a RISC machine having a conventional 32-bit fixed-length instruction format since the instruction format has the fixed length. Consequently, such problem that a memory needs to be increased in circuit scale can be evaded.

10. 发明专利

JPH06149545A SEMICONDUCTOR INTEGRATED CIRCUIT PROVIDED WITH CPU AND MULTIPLIER 失效
公开(公告)号：JPH06149545A
公开(公告)日：1994-05-27
申请号：JP29677892
申请日：1992-11-06
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KISHI KAZUMASA , MASUMURA SHIGEKI , NAKAMURA HIDEO , NOGUCHI YOSHIKI , KAWASAKI SHUNPEI , AKAO YASUSHI
IPC分类号： G06F7/52 , G06F7/506 , G06F7/523 , G06F9/302 , G06F9/32 , G06F9/38 , G06F15/78
摘要： PURPOSE:To provide a semiconductor integrated circuit capable of facilitating design change matched with the target performance of a multiplier and directly transferring data between a memory and the multiplier. CONSTITUTION:This circuit is provided with a CPU 1, buses 5 and 4, the memory 3 accessed by the CPU 1, the multiplier 2 and a command signal line 6 for transferring the command of a multiplication instruction relating to read data from the CPU 1 to the multiplier 2 while reading the memory 3 from the CPU 1 through the bus 4. Since the CPU 1 and the multiplier 2 are different module constitution, the CPU 1 is not related to the performance change of the multiplier 2 and design change layout is facilitated. Since the command of the multiplication instruction relating to the read data is transferred from the CPU 1 to the multiplier 2 while reading the memory 3 from the CPU 1, the data can be directly transferred between the memory 3 and the multiplier 2.

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