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1. 发明专利

JPS62242243A INFORMATION PROCESSOR 失效
公开(公告)号：JPS62242243A
公开(公告)日：1987-10-22
申请号：JP8544286
申请日：1986-04-14
申请人： HITACHI LTD
发明人： WATANABE HIROSHI , KURAKAZU KEIICHI , KASHIWAGI YUUGO , TOYAMA KEISUKE , NOJIRI TORU
IPC分类号： G06F15/00 , G06F9/30 , G06F9/318 , G06F9/355 , G06F9/40 , G06F9/42 , G06F9/46 , G06F9/48 , G06F12/00 , G06F12/02
摘要： PURPOSE:To simplify the allocating work of registers at the time of preparation of a program and to speed up processing by designating registers used in the execution of an instruction by the combination of the designation of an area register that indicates the position of a register area and the designation of register displacement that indicates relative position in the register area. CONSTITUTION:An area registering section 13 and a register displacement section 14 of (l) bits in length are included in an instruction register designating section 12. When the value of the area registering section 13 is (i), (i) is sent to the area register selector circuit 20 of a register access mechanism 5, and an Ri register 21 in a register group 3 is selected as an area register, and its value bi is sent to a register pointer 22. Out of register addresses of L bits sent to a register selector circuit 31 lower (l) bits are made to an OR obtained by inputting the content of lower (l) bits part 24 of the register pointer 22 and the content of the register displacement section 14 to an OR circuit 30, and upper L-l bits of register addresses are made to the value of upper L-l bits part 23 of the register area pointer 22.

2. 发明专利

JPS62121560A MEMORY MANAGEMENT SYSTEM 失效
公开(公告)号：JPS62121560A
公开(公告)日：1987-06-02
申请号：JP26113585
申请日：1985-11-22
申请人： HITACHI LTD
发明人： KASHIWAGI YUUGO
IPC分类号： G06F12/12
摘要： PURPOSE:To reduce the number of page faults by replacing a block corresponding to the maximum or minimum quantity of analog when the required block is not present in a main memory means by a desired block in a secondary memory means. CONSTITUTION:Referring analog elements Ao-An changing the analog quantity with the lapse of time are matched every page of the main memory, the page absent in the main memory MRY1 during the reference is replaced by the page corresponding to the referring analog element of the largest (or the smallest) quantity of the analog and the analog element corresponding to the referred page is reset (or set) during the reference. Thereby, the replacement of the page is carried out in the sequence of the pages which are not referred for the longest period in the main memory, namely, in an algorism very near to an ideal LRU algorism, the number of the page faults is reduced and a burden of an operating system is reduced.

3. 发明专利

JP2000235510A PROCESSOR AND COMPILE PROGRAM RECORDING MEDIUM FOR THE PROCESSOR 失效
公开(公告)号：JP2000235510A
公开(公告)日：2000-08-29
申请号：JP3550199
申请日：1999-02-15
申请人： HITACHI LTD
发明人： NAKANO SADASHIGE , NISHIMOTO JUNICHI , MATSUI SHIGESUMI , TSUNODA MASANOBU , YONEYAMA KOJI , KANDA SHINYA , KASHIWAGI YUUGO
IPC分类号： G06F11/34
摘要： PROBLEM TO BE SOLVED: To obtain a processor capable of quickly collecting trace data. SOLUTION: Plural trace instructions for specifying a register for storing data to be outputted as trace data are integrated in a source program to be analyzed. At the time of executing a certain trace instruction during the execution of an object program obtained by compiling the source program, a CPU 110 supplies data stored in a general register specified by the instruction, the instruction address of the trace instruction and a trace command to an internal bus group 10 arranged between the CPU 1 10 and a cache unit 111. A trace unit 20 enters one of the groups of instruction addresses and trace data included in the internal bus group 10 as one trace information and supplies the information to a hardware simulator. The cache unit 111 is constituted so as not to respond to the trace command.

4. 发明专利

JPH06309133A CONTROL METHOD FOR OPERATING SYSTEM 失效
公开(公告)号：JPH06309133A
公开(公告)日：1994-11-04
申请号：JP9637793
申请日：1993-04-23
申请人： HITACHI LTD
发明人： FUKUSHIMA YOKO , KASHIWAGI YUUGO
IPC分类号： G06F3/14 , G06F3/048 , G06F9/46
摘要： PURPOSE:To precisely predict an operation to be executed at the next time by a user and to automatically perform the default of a menu corresponding to the user. CONSTITUTION:For example, when the user performs program development, the operation history of the user is stored in a data file 2 for a prescribed time after an ID number is inputted. An automatic customizing part 3 refers to the content of the data file 2, and decides what menu with high probability to be selected or what menu with high probability to be selected following after a certain menu is selected is, and changes the content of a system environmental file 4 so as to automatically perform the default of the menu.

5. 发明专利

JPH05197546A MICROCOMPUTER AND DIVIDING CIRCUIT 失效
公开(公告)号：JPH05197546A
公开(公告)日：1993-08-06
申请号：JP15452592
申请日：1992-05-21
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI VLSI ENG
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38
摘要： PURPOSE:To decrease program capacity or improve the utilization efficiency of a program memory by employing a fixed length instruction format which is smaller in the number of bits than the maximum length of data words supplied to an instruction executing means. CONSTITUTION:The microcomputer has RISC(reduced instruction set type computer) type architecture and has the fixed length instruction format. When data and instructions are transferred, a bus, e.g. an internal data bus IDB is of 32-bit constitution, but the instructions are in 16-bit fixed length instruction format. Then 16-bit instruction buffers (instruction queue) IRH and IRL store the instructions, one by one, and the instructions are loaded respectively in a single instruction fetch cycle. The instructions are transferred in 32-bit units through the internal data bus IDB and then loaded in an instruction register IR1 through a multiplexer MPX. Then the 16-bit instruction register IR1 holds the instructions present in an instruction decoding stage.

6. 发明专利

JP2000029692A CENTRAL PROCESSOR 失效
公开(公告)号：JP2000029692A
公开(公告)日：2000-01-28
申请号：JP13977299
申请日：1999-05-20
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F9/355 , G06F9/34
摘要： PROBLEM TO BE SOLVED: To decrease program capacity or increase the efficiency of a program memory and to reduce the system cost by adopting a fixed-length instruction format whose bit number is less than the maximum data word length supplied to an instruction executing means. SOLUTION: An instruction register IR1 holds an instruction present at an instruction decoding means. The decoding results of a source register decoder SRD and a destination register decoder DRD are used to specify which of general register R0H, R0L to R15H, and R15L included in an execution part EXEC is selected. With a data transfer instruction, data stored in the address obtained by adding a value of displacement and the value of an address stored in a program counter are transferred to one of registers. In this case, the fixed-length instruction format whose bit number is less than the maximum data word length supplied to the instruction execution means is adopted.

7. 发明专利

JPH06168140A PROGRAM CONVERTER 失效
公开(公告)号：JPH06168140A
公开(公告)日：1994-06-14
申请号：JP34163492
申请日：1992-11-27
申请人： HITACHI LTD
发明人： SAWA NORIKO , KASHIWAGI YUUGO , NAGAYAMA HIROMI , YAJIMA HIROSHI , TAWARA YASUHIRO , CHAGI HIDEAKI
IPC分类号： G06F9/45
摘要： PURPOSE:To output an object code of size smaller than ever and with execution speed faster than ever when a program described in high-level language is translated. CONSTITUTION:A target machine is provided with the object code which makes access data in a stack frame 21 with a relative address setting the value of a stack pointer SP indicating the stack area of the stack frame as reference. At this time, a code generating means which stacks a local variable area 24 and a temporary area 23 on a register saving area 25 is employed in the stack frame 21. The temporary area and the local variable area used frequently are arranged in the neighborhood of a value indicated by the stack pointer, and those areas can be surely accessed with stack pointer correspondence, and the size of the object code can be reduced.

8. 发明专利

JPH0695921A SIMULATION METHOD AND PROGRAM DEBUGGING SYSTEM 失效
公开(公告)号：JPH0695921A
公开(公告)日：1994-04-08
申请号：JP27242292
申请日：1992-09-16
申请人： HITACHI LTD
发明人： KASHIWAGI YUUGO , HAYASHI TSUTOMU , SHINODA YOSHIHIRO
IPC分类号： G06F9/455 , G06F11/28
摘要： PURPOSE:To speed up processing in the case of simulating or debugging the execution of a program for a target computer by a host computer. CONSTITUTION:A compiler 2 generates an object information program 6 from a source program 1 for the target computer. The program 6 is obtained by translating instruction strings (including no jump instruction, branch instruction, or restoring instruction from a subroutine on the way) for the target computer which can be sequentially executed into instruction strings for the host computer 3. Since simulation is executed in each translated instruction string, the convensional overhead of instruction interpretation as data for the execution of one step can be reduced and the speed-up of simulation can be attained.

9. 发明专利

JPH02156375A HYBRID TYPE FUNCTION CALCULATING METHOD 失效
公开(公告)号：JPH02156375A
公开(公告)日：1990-06-15
申请号：JP30996888
申请日：1988-12-09
申请人： HITACHI LTD
发明人： KAWASAKI SHUNPEI , TATEZAKI JIYUNICHI , NAKAGAWA NORIO , KASHIWAGI YUUGO
IPC分类号： G06F7/537 , G06F7/483 , G06F7/52 , G06F7/53 , G06F7/535 , G06F7/552 , G06F17/17
摘要： PURPOSE:To improve operational efficiency by calculating the approximate solution of a square root by means of a Newton-Raphson method, correcting a bit array by means of an adder/multiplier, when the accuracy of a strict solution is insufficient, correcting only the high-order bit array, restarting dichotomy from the corrected position, and finally executing a rounding processing. CONSTITUTION:To obtain highly efficient square root argorithm, the approximate solution is calculated by the Newton-Raphson method (step P1), and the bit array is corrected with the use of the adder/multiplier (step P2). When the accuracy of the approximate solution is sufficient, the all bits are accurately corrected by a correcting processing. When the accuracy of the approximate solution is insufficient, only the high-order bit arrays are corrected, and the dichotomy is restarted from the corrected position (step P3). In either case, the rounding processing is finally executed (step P4). Thus, the efficiency of an operation to obtain the strict solution of the square root in a prescribed floating decimal point format can be improved.

10. 发明专利

JP2001344127A SYSTEM DEVELOPING METHOD, STORAGE MEDIUM, INFORMATION PROCESSOR, INFORMATION TERMINAL DEVICE, INFORMATION PROCESSING SYSTEM, AND INFORMATION PROCESSING METHOD 失效
公开(公告)号：JP2001344127A
公开(公告)日：2001-12-14
申请号：JP2000166468
申请日：2000-05-31
申请人： HITACHI LTD
发明人： KASHIWAGI YUUGO
IPC分类号： G06F11/28 , G06F9/44 , G06F9/45 , G06F11/36
摘要： PROBLEM TO BE SOLVED: To reduce the cost of a data processing system providing services to clients or information terminal devices through a network or the like and to simplify the communications with the clients. SOLUTION: When an information processing system having a server 40 providing services after receiving the requests for services through a transmission line or the network 44 is assumed, the server provides services in response to address information after receiving the address information such as command addresses of address spaces from the clients while the program of the server is not called from the clients 41, 42, 43. Since this protocol is employed, the communication process between the server and the clients is simplified, and the data processing system providing services to the clients or the information terminal devices through the network or the like can be realized at a low cost.

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