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1. 发明专利

JP2002125172A VIDEO SIGNAL MAGNIFICATION REDUCTION CIRCUIT AND TELEVISION RECEIVER USING IT 失效
公开(公告)号：JP2002125172A
公开(公告)日：2002-04-26
申请号：JP2000316899
申请日：2000-10-17
申请人： HITACHI LTD
发明人： TAKAHASHI TETSUO , TORIGOE SHINOBU , ONO KOICHI , IWATA KENICHI , KURODA YOSHIAKI
IPC分类号： H04N5/46 , G09G5/36 , H04N3/22 , H04N3/27
摘要： PROBLEM TO BE SOLVED: To provide a video signal magnification reduction circuit that suppresses deterioration in the image quality in the case of outputting a signal with an aspect ratio of 4:3 from a device with an aspect ratio of 16:9. SOLUTION: The video signal magnification reduction circuit is provided with a magnified coefficient/reduced coefficient generating means that takes five states resulting from combinations of cases where a magnification coefficient is decreased, constant or increased and a reduction coefficient is increased, constant or decreased with attendance on a change in a horizontal position of a video signal, a video horizontal reduction means that used the reduction coefficient so as to reduce the input video signal at a reduction rate of 1/(1+reduction coefficient), and a video horizontal magnification means that uses the magnification coefficient to magnify the signal subjected to horizontal reduction at a magnification factor of 1/(1-magnification coefficient).

2. 发明专利

JP2000251470A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2000251470A
公开(公告)日：2000-09-14
申请号：JP5244499
申请日：1999-03-01
申请人： HITACHI LTD
发明人： NAKAMOTO TAKASHI , TANAKA CHIKASHI , IWATA KENICHI
IPC分类号： G11C11/401 , G06F12/06 , G11C11/407
摘要： PROBLEM TO BE SOLVED: To improve the efficiency of the operation for obtaining continuous data stored in plural memory banks from an arbitrary position. SOLUTION: A buffer writing circuit 52 writes the data, which are read from a synchronous memory 7 by a burst access while switching memory banks, into a buffer memory in a word unit. The memory 7 stores continuous data for every burst access continuous access word number while successively switching the memory banks. A buffer writing circuit 52 inputs address information A9 and A2 to A0, that specify memory banks and a burst access leading word position, changes the generating order of writing addresses in accordance with the number of words to the leading word specified by address information against the leading position in the range of the word number corresponding to the bank number magnification of the continuous access word number by the burst access, changes the data language from the memory bank into an original data arrangement order and writes the data into a data buffer and executes a writing control.

3. 发明专利

JP2003102013A DECODER, ENCODER, AND ENCODING DECODER 审中-公开
公开(公告)号：JP2003102013A
公开(公告)日：2003-04-04
申请号：JP2001289082
申请日：2001-09-21
申请人： HITACHI LTD
发明人： IWATA KENICHI , WATANABE HIROKI
IPC分类号： H04N19/50 , H03M7/30 , H04N19/423 , H04N19/46 , H04N19/463 , H04N19/625 , H04N19/70 , H04N19/91 , H04N7/32
摘要： PROBLEM TO BE SOLVED: To provide an encoding decoding technology capable of contributing to reduction in data amounts and improvement of the decoding processing efficiency. SOLUTION: A decoder (9) for receiving and decoding encoded data, where an information frame is divided into the blocks and encoded, subjected to inter- frame motion compensation in the unit of a plurality of blocks, is provided with a decoding means (22) for decoding a code word indicative of areas of blocks without the encoded data in the unit of a plurality of blocks with a smaller scale than that of the information frame, and refers to the information of the areas decoded by the decoding means so as to attain information reproduction of the blocks without the encoded data. The data amount can be reduced in comparison with the case that none of the encoded data in the unit of blocks is indicated. Decoding the code word can recognize the arrangement of the blocks without the encoded data so as to attain application of parallel processing to DMA transfer control or the like for the information reproduction with respect to the blocks without the encoded data in parallel with decoding the block data with the encoded data.

4. 发明专利

JP2002125200A MOVING PICTURE FORMAT CONVERTER 失效
公开(公告)号：JP2002125200A
公开(公告)日：2002-04-26
申请号：JP2000315281
申请日：2000-10-16
申请人： HITACHI LTD
发明人： IWATA KENICHI , ONO KOICHI , TORIGOE SHINOBU , KURODA YOSHIAKI , TAKAHASHI TETSUO
IPC分类号： H04N5/262 , H04N7/01
摘要： PROBLEM TO BE SOLVED: To provide a means that outputs both moving picture signals of analog and digital broadcast programs to display devices with different formats. SOLUTION: The moving picture format converter of this invention is applied to a digital broadcast receiver provided with a horizontal/vertical size conversion means that magnifies or reduces an input moving picture signal at an optional magnification in horizontal/vertical direction, with a data buffer that stores a data quantity of a horizontal size of the input moving picture signal, with a means that selects each input signal, and with a means that selects a display output signal, allows the selection means to select the signal in a way of minimizing the data quantity received by the data buffer and the vertical size conversion means depending on an image format conversion operating mode, and allows the data buffer 23(24) to selectively act like a write buffer 231 and a read buffer 232 for access to a field memory to delay the input signal by a prescribed time or like one line buffer through the cascade connection of them.

5. 发明专利

JP2000347638A OSD DEVICE, CODING VIDEO DECODING DEVICE USING IT, AND DIGITAL BROADCAST RECEIVING DEVICE USING THE DECODING DEVICE 失效
公开(公告)号：JP2000347638A
公开(公告)日：2000-12-15
申请号：JP15926299
申请日：1999-06-07
申请人： HITACHI LTD
发明人： KOMI HIRONORI , TERUI KOICHI , IWATA KENICHI , TORIGOE SHINOBU , OKU MASUO , KOREEDA HIROYUKI
IPC分类号： G09G5/00 , G09G5/12 , G09G5/377 , G09G5/391 , H04N5/445 , H04N5/46 , H04N7/025 , H04N7/03 , H04N7/035
摘要： PROBLEM TO BE SOLVED: To use a common font set to generate a common image plane to make synthesis possible even if resolution of connected display is changed by reading out graphic data from a memory means, and providing an image format conversion means magnifying/contracting the horizontal or vertical picture element number of the graphic data before transferring to a picture element synthesis means. SOLUTION: A bit stream input to a video decoding device 1 is input from a terminal 151 to a MPEG video decoding circuit 11, and transferred to a memory 2 through a memory controller 14. A CLUT reference circuit 131 reads out data from the memory 2 through the memory controller 14, before the timing synthesizing OSD graphic data into a decoding image by a synthesis circuit 133. The brightness and the color difference information of respective picture elements are sent to an OSD image format conversion circuit 132, and as for respective brightness (Y-component), color difference component (Cb, Cr component), contraction of the number of horizontal picture element and contraction of the number of vertical picture elements are processed.

6. 发明专利

JP2008003708A Image processing engine and image processing system including the same 有权
标题翻译：图像处理发动机和图像处理系统，包括它们
公开(公告)号：JP2008003708A
公开(公告)日：2008-01-10
申请号：JP2006170382
申请日：2006-06-20
申请人： Hitachi Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立製作所
发明人： HOSOKI KOJI , EHAMA MASAKAZU , NAKADA KEIMEI , IWATA KENICHI , MOCHIZUKI SEIJI , YUASA TAKASHI , KOBAYASHI YUKIFUMI , SHIBAYAMA TETSUYA , UEDA KOJI , NOBORI MASAKI
IPC分类号： G06F9/34 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/30087
摘要： PROBLEM TO BE SOLVED: To resolve the problem that the power consumption is increased by occurrence of an instruction memory read at every cycle because of supply of one or more instructions in one cycle with respect to instructions issued from a CPU and is increased by the occurrence of simultaneous access of instruction memories at every cycle because of the increase in number of instruction memories for a multiprocessor configuration.
SOLUTION: A means is provided which designates two-dimensional source registers and destination registers to an operand of an instruction, and an operation using a plurality of source registers is executed in a plurality of cycles to obtain a plurality of destinations. In an instruction to obtain destinations by using a plurality of source registers and consuming a plurality of cycles, a data rounding computing unit is connected to the last step of a pipeline. Furthermore, a plurality of CPUs are connected in series and use shared instruction memories in common. In this case, a field for controlling synchronization between adjacent CPUs is provided in an instruction operand of each CPU, whereby synchronization control is performed.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：解决由于在每个周期读取指令存储器而产生的功耗增加的问题，因为相对于从CPU发出的指令在一个周期内提供一个或多个指令并增加由于多处理器配置的指令存储器数量的增加，在每个周期的同时存取指令存储器的发生。解决方案：提供一种将二维源寄存器和目标寄存器指定到指令的操作数的装置，并且以多个周期执行使用多个源寄存器的操作以获得多个目的地。在通过使用多个源寄存器并消耗多个周期来获取目的地的指令中，数据舍入计算单元连接到流水线的最后一个步骤。此外，多个CPU串联连接并共同使用共享指令存储器。在这种情况下，在每个CPU的指令操作数中提供用于控制相邻CPU之间的同步的字段，由此执行同步控制。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2000004441A MOTION DETECTION METHOD AND DEVICE 失效
公开(公告)号：JP2000004441A
公开(公告)日：2000-01-07
申请号：JP9958299
申请日：1999-04-07
申请人： HITACHI LTD
发明人： WATANABE HIROMI , IWATA KENICHI , HATAE HIROSHI
IPC分类号： H04N19/50 , H03M7/36 , H04N19/51 , H04N19/513 , H04N19/523 , H04N19/57 , H04N7/32
摘要： PROBLEM TO BE SOLVED: To enhance the transfer efficiency of data by reducing a read time and an arithmetic time of the data used for detecting a motion of a picture. SOLUTION: A motion-detected block S1 is divided into plural division- motion-detected blocks whose pixel positions differ from each other (811), and a degree of approximation between each of plural division-motion-detected blocks and a same reference image block (824) segmented from a motion detection range of a reference picture is obtained in parallel by arithmetic sections (816-819), and the division-motion-detected block with the highest degree of approximation is decided among the respective degrees of approximation (823). A vector corresponding to the division-motion-detected block is detected as a motion vector (S82) of the block of the picture whose motion is an object of detection.

8. 发明专利

JPH07306665A SIMPLIFIED POWER MANAGEMENT SYSTEM FOR DISPLAY DEVICE 失效
公开(公告)号：JPH07306665A
公开(公告)日：1995-11-21
申请号：JP10045694
申请日：1994-05-16
申请人： HITACHI LTD , HITACHI COMPUTER ELECTRONIC
发明人： OSHIMA TOSHIYOSHI , IWAI MASAHIRO , KOGOORI FUMIHIRO , IWATA KENICHI
IPC分类号： G09G5/00
摘要： PURPOSE:To realize the simplified power saving of a display device by controlling an image/synchronizing signal and power supply to the display device from the outside on a host device and the display device without power management function, and contribute to the reduction of carbon dioxide, sulfur dioxide, nitrogen dioxide dis charged in large quantities from an electric power plant through the realization of power saving in addition to reducing the cost of electric power and the purhcase expanses of new hardware and software for users. CONSTITUTION:A power management system for a host device 9 and a display device 6 existing without power management function can realize simplified power saving by monitoring a keyboard and mouse signals S1, S2 from the outside so as to control an image/synchronizing signal S5 and power supply S6 to the display device 6. In this power management system, a synchronous separating/synthesizing circuit that can cope with a composite signal system, one of signal systems for the display device is provided at a synchronizing signal output circuit 5, at the input part from the host device 9 and at the output part to the display device 6, and the unused state of the host device 9 can be shifted to three kinds of power-saving modes easily by the optionally set elapsed time.

9. 发明专利

JP2002300588A IMAGE-DECODING METHOD AND APPARATUS 失效
公开(公告)号：JP2002300588A
公开(公告)日：2002-10-11
申请号：JP2001104272
申请日：2001-04-03
申请人： HITACHI LTD
发明人： KATAGAI TOSHIHARU , WATANABE HIROMI , HASE AKIRA , IWATA KENICHI
IPC分类号： H04N19/50 , G06T9/00 , H03M7/36 , H04N19/102 , H04N19/134 , H04N19/172 , H04N19/196 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/503 , H04N19/51 , H04N19/577 , H04N19/61 , H04N19/625 , H04N7/32
摘要： PROBLEM TO BE SOLVED: To reduce load on image-decoding processing. SOLUTION: The image-decoding apparatus comprises an image type decoding section 104 for detecting a bidirectional prediction coding frame obtained, based on a first frame in the past and a second frame in the future in an image display order, a code read jump circuit 103 for abbreviating the decoding of the bidirectional prediction coding frame based on the detection result, and means 150, 160, 170, and 180 allocating what is obtained by decoding the coded data in the first frame or what is obtained by decoding the coded data of the second frame instead of the result output of the decoding, when the decoding to the bidirectional prediction coded frame is abbreviated, thus abbreviating the decoding to the bidirectional prediction coded frame and hence reducing the load on image decoding.

10. 发明专利

JP2000242549A LINE MEMORY CONSTRUCTING METHOD AND LINE MEMORY 失效
公开(公告)号：JP2000242549A
公开(公告)日：2000-09-08
申请号：JP4252699
申请日：1999-02-22
申请人： HITACHI LTD
发明人： IWATA KENICHI , KOMI HIRONORI , ONO KOICHI
IPC分类号： G06F12/00 , G06F12/02 , G06T1/60 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To perform the format conversion and resolution conversion processing of an image signal by a line memory of a small capacity. SOLUTION: This line memory consists of plural line segments and a register group showing the connection information of the line segments, and a line memory 4 needed by each of signal processing parts 1 and 2 to obtain a delay signal is realized by cascading one or more line segments. A register showing the connection information of the line segments consists of leading line segment setting registers 401 and 402 setting line segments to first accessed for the plural parts 1 and 2 and the next line segment setting registers 403 and 404 setting, for the plural line segments, line segments that should next be accessed by the connected parts 1 and 2. Delay circuits and line buffers having various lengths are realized by adopting a line memory configuration having a link structure, and the plural signal processing parts in a signal processing integrated circuit share the shared line memory.

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