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1. 发明专利

JP2003255904A DISPLAY DEVICE AND DRIVING CIRCUIT FOR DISPLAY 有权
公开(公告)号：JP2003255904A
公开(公告)日：2003-09-10
申请号：JP2002055165
申请日：2002-03-01
申请人： HITACHI LTD
发明人： KUDO YASUYUKI , AKAI RIYOUJIN , DAIMON KAZUO , MATSUDO TOSHIMITSU , HIGA ATSUHIRO
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To solve the problem that, in a liquid crystal display device which is provided with a switch group for distributing (demultiplexing) column voltages to be outputted from a column driving circuit and for outputting the demultiplexed column voltages to column electrodes of a pixel part, when the output phase of a column voltage is more delayed than control signals S1 to S3 of a switch, after a column voltage being in a previous state is once applied on column electrodes, an essential column voltage is applied on the column electrodes, and as a result, an unnecessary waveform fluctuation is caused in the application voltage of the column voltage and this becomes a cause with which power consumption is increased in the display device. SOLUTION: Non-overlap periods when all of control signals of switches become 'low' are provided to the display device and the timing of respective signals are stipulated so that column voltages are changed in these periods. In short, column voltages are made to be changed in a state when the switch group are all in OFF states. Thus, a phenomenon in which a previous column voltage is once applied on the column electrodes is avoided in the display device and the unnecessary voltage fluctuation is prevented and the increasing of the power consumption can be avoided in the display device. COPYRIGHT: (C)2003,JPO

2. 发明专利

JPH0420016A CLOCK GENERATOR AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0420016A
公开(公告)日：1992-01-23
申请号：JP12362490
申请日：1990-05-14
申请人： HITACHI LTD
发明人： SUGINO KIMIHIRO , DAIMON KAZUO
IPC分类号： H03K3/03 , H03L7/099
摘要： PURPOSE:To suppress an oscillating frequency from a ring oscillator low by including the ring oscillator comprising of an odd number of stages of delay circuits into a voltage controlled oscillator circuit and extracting outputs of the plural delay circuits included in the ring oscillator separately as clock signals of plural phases directly. CONSTITUTION:A clock generator 2 consists of a frequency multiplier circuit employing a PLL circuit and its voltage controlled oscillator circuit 22 includes the ring oscillator in which odd number of stages of voltage controlled type delay circuits whose delay is controlled by a voltage are in feedback connection. Outputs of the plural delay circuits included in the ring oscillator are given directly separately as plural phases of clock signals to a pulse generating logic circuit 24. Thus, the oscillating frequency of the ring oscillator is suppressed lower and the power consumption in the voltage controlled oscillator circuit is reduced.

3. 发明专利

JPH01128604A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01128604A
公开(公告)日：1989-05-22
申请号：JP28532587
申请日：1987-11-13
申请人： HITACHI LTD
发明人： ENDO TAKEFUMI , DAIMON KAZUO
IPC分类号： H03F3/345 , H03F3/34
摘要： PURPOSE:To improve a PSRR (Power Supply Rejection Ratio) characteristic as an operational amplifier circuit by providing a capacitor for coupling, which has prescribed electrostatic capacity, in an interval with the power source voltage or grounding potential of a circuit. CONSTITUTION:A capacitor C1 for coupling is provided between the gate of an MOSFET Q2 and the power source voltage of the circuit. Noise to be overlapped to a power source voltage Vcc of the circuit by some causes is alternately transmitted through the capacitor C1 to the gate of the driving MOSFET Q2. Namely, for the noise to be overlapped to the power source voltage Vcc of the circuit, the gate potential of the driving MOSFET Q2 is almost in-phase- changed in a high frequency area. Accordingly, although the noise is overlapped to the power source voltage Vcc of the circuit, the voltage between source and gate of the driving MOSFET Q2 goes to be a constant value. Thus, the value of an operating current, which is supplied to differential MOSFETs Q3 and Q4, is stabilized and the PSRR characteristic of an operational amplifier circuit OA1 is improved.

4. 发明专利

JPS63294132A A/D CONVERTER 失效
公开(公告)号：JPS63294132A
公开(公告)日：1988-11-30
申请号：JP12826487
申请日：1987-05-27
申请人： HITACHI LTD
发明人： DAIMON KAZUO
IPC分类号： H03M3/02
摘要： PURPOSE:To prevent the deterioration of S/N of an A/D converter, by providing plural integrators on the pre-stage of a comparator which compares the output of the integrators with a reference value and allowing each integrator to operate at clocks of a frequency which is 1/n of the frequency of the operating clock of the comparator. CONSTITUTION:Two integrators 2a and 2b are provided on a comparator 3 and the input of each integrator 2a and 2b is sampled at clocks whose frequency is 1/2 of a desired frequency whose the phase is shifted by a half period. Since one integrator 2b can start its integrating operation while the output of the other integrator 2a is compared at the comparator 3, the one integrator can be operated with the frequency which is 1/2 of the sampling frequency when attention is paid to the one integrator and the degree of time to spare to the settling time becomes larger. Therefore, deterioration of S/N due to insufficient speeds of the integrators can be prevented.

5. 发明专利

JPS63211826A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63211826A
公开(公告)日：1988-09-02
申请号：JP4250387
申请日：1987-02-27
申请人： HITACHI LTD
发明人： DAIMON KAZUO , FUJII FUMIAKI
IPC分类号： H03M1/00 , H04B14/04 , H04Q3/42
摘要： PURPOSE:To contrive the improvement of the S/N of a digital communication system including a CODEC by operating the titled circuit according to an internal clock signal generated by a built-in PLL circuit and operating only a buffer of a PCM input/output circuit according to an external clock signal. CONSTITUTION:An A/D, D/A converting circuit of a CODEC and a compression/ expanding circuit or the like of a pulse code modulation PCM input/output circuit PCMI/O are operated according to the internal clock signal generated by a phase locked loop PLL circuit PLL and only the buffer of the PCM input/ output circuit PCMI/O is operated according to an external clock signal. Thus, since almost all circuit blocks of the CODEC formed on one semiconductor substrate is operated by the internal clock signal of the same system, the noise in the voice band caused according to a comparatively small frequency difference between the internal clock signal including jitter and the external clock signal not including jitter is suppressed and the S/N of the communication system including the CODEC is improved.

6. 发明专利

JPS6352517A PLL CIRCUIT 失效
公开(公告)号：JPS6352517A
公开(公告)日：1988-03-05
申请号：JP19531886
申请日：1986-08-22
申请人： HITACHI LTD
发明人： OKAZAKI TAKAO , DAIMON KAZUO
IPC分类号： H03L7/10 , H03L7/107
摘要： PURPOSE:To decrease the pull in time at the start of operation and to prevent the increase in jitter by decreasing a high frequency gain, increasing a capacitance of a loop filter and decreasing a current of a current source for charge/ discharge after a prescribed time elapses from the start of phase control. CONSTITUTION:An output signal S of a timer circuit TM is fed to a current changeover circuit and also to the loop filter LPF. Until a prescribed time elapses from the start of the phase control of a PLL circuit, the output signal S of the circuit TM is at a low level, the high frequency gain of the PLL circuit is increased, and after a prescribed time elapses, the output signal S goes to a high level, the high frequency gain of the PLL circuit is decreased, MOSFETs Q8, Q9 of the LPF are turned on, and a capacitor C2 having a comparatively larger capacitance is connected to an output code and an output terminal of the LPF. Moreover, MOSFET Q3 or Q4 is turned on in this case, a charging current source IS3 and a discharge current source IS4 having a comparatively smaller current is connected to the output node and the output terminal of the LPF.

7. 发明专利

JPS61245628A PHASE LOCKED LOOP CIRCUIT 失效
公开(公告)号：JPS61245628A
公开(公告)日：1986-10-31
申请号：JP8639585
申请日：1985-04-24
申请人： HITACHI LTD
发明人： DAIMON KAZUO
IPC分类号： H03L7/10
摘要： PURPOSE:To shorten the pull-in time by increasing the high frequency gain for a fixed period of time needed for pull-in of a phase locked loop (PLL) circuit and then reducing the high frequency gain. CONSTITUTION:An up-current and a down-current which are larger and smaller than the center current which is kept constant for a fixed period of time from the start of a timer circuit TM are flowed according to the up/down output signal of a phase comparator PFC and the output signal of the circuit TM which is started with the PLL action start signal. The current switching circuits IV5-8 are added to reduce the up-current and increase the down-current after a fixed period of time. Then capacitors C1 and C2 are charged and discharged by the synthetic current of the output current of the current switching circuit and the current produced in response to the control voltage generated by a loop filter LPF. This shortens the pull-in time and stabilizes the working of a PLL circuit.

8. 发明专利

JP2006309272A Display device 有权
标题翻译：显示设备
公开(公告)号：JP2006309272A
公开(公告)日：2006-11-09
申请号：JP2006212741
申请日：2006-08-04
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KUDO YASUYUKI , AKAI RIYOUJIN , DAIMON KAZUO , KUROKAWA KAZUNARI , HIGA ATSUHIRO
IPC分类号： G09G3/36 , G02F1/133 , G09G3/20
摘要： PROBLEM TO BE SOLVED: To provide a power supply device capable of reducing power consumption and enhancing convenience of a user and its liquid crystal display device.
SOLUTION: This invention is equipped with a setting register 100 which sets amplitude and a voltage level between drive voltage of a common electrode and non-scanning period voltage of a scanning line, an amplitude reference generation circuit 101 which generates amplitude reference voltage between the drive voltage of the common electrode and the non-scanning period voltage of the scanning line according to the set value, a VcomH reference generation circuit 102 and a VcomL generation circuit 100 which perform AC drive of the common electrode by the amplitude and at the voltage level determined from the amplitude reference voltage and the set value, a VgoffH generation circuit 104 and a VgoffL reference generation circuit 105 which generate non-scanning period voltage of the scanning line with the same phase and the same amplitude as the drive voltage of the common electrode by the amplitude and at the voltage level determined from the amplitude reference voltage and the set value.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够降低用户及其液晶显示装置的功耗并提高便利性的电源装置。解决方案：本发明配备有设置寄存器100，其设置公共电极的驱动电压和扫描线的非扫描周期电压之间的振幅和电压电平;幅度参考生成电路101，其产生幅度参考电压在公共电极的驱动电压和扫描线的非扫描周期电压之间根据设定值，VcomH基准产生电路102和VcomL产生电路100，其通过振幅和从幅度参考电压和设定值确定的电压电平，VgoffH生成电路104和VgoffL参考生成电路105，VgoffH生成电路104和VgoffL参考产生电路105产生与驱动电压相同且相同振幅的扫描线的非扫描周期电压公共电极由幅度和电压电平根据幅度参考电压和设定值确定。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2005049868A Display driving device 有权
标题翻译：显示驱动器件
公开(公告)号：JP2005049868A
公开(公告)日：2005-02-24
申请号：JP2004212464
申请日：2004-07-21
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KUDO YASUYUKI , AKAI RIYOUJIN , DAIMON KAZUO , KUROKAWA KAZUNARI , AIZAWA HIROMI
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To achieve higher image quality and versatility by constituting a display driving device in such a manner that the gamma adjustment meeting the individual characteristics of liquid crystal panels can be most adequately and easily adjusted by three kinds of adjustments; amplitude, tilt and fine adjustment in the adjustment of the gamma characteristics.
SOLUTION: The display driving device is equipped with a plurality of rudder resistors 326 to 330 which perform resistance division of a reference voltage, a resistance division circuit which performs the resistance division of the voltages subjected to the resistance division by the rudder resistors, selector circuits 308 to 313 which select gray scale voltages from the voltages subjected to the resistance division by the resistance division circuit, a first variable resistor 322 which exists between the rudder resistors and the reference voltage, a second variable resistor 321 which exists between the rudder resistors and the ground, and third variable resistors 323 and 324 which exist between the plurality of of the rudder resistors.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过构成显示驱动装置来实现更高的图像质量和多功能性，使得能够通过三种调整来最充分和容易地调整满足液晶面板的各个特性的伽马调整; 幅度，倾斜和微调等方面的伽马特性的调整。解决方案：显示驱动装置配备有执行参考电压的电阻划分的多个舵电阻器326至330，执行由舵电阻器进行电阻分割的电压的电阻分割的电阻分割电路选择电路308至313，其从由电阻分割电路进行电阻划分的电压中选择灰度电压;存在于舵电阻器和基准电压之间的第一可变电阻器322;位于第二可变电阻器321之间的第二可变电阻器321，方向舵电阻和地，以及存在于多个方向舵电阻之间的第三可变电阻器323和324。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2002366114A POWER UNIT AND LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JP2002366114A
公开(公告)日：2002-12-20
申请号：JP2001171888
申请日：2001-06-07
申请人： HITACHI LTD
发明人： KUDO YASUYUKI , AKAI RIYOUJIN , DAIMON KAZUO , KUROKAWA KAZUNARI , HIGA ATSUHIRO
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To solve the problem of a conventional liquid crystal display device that a power circuit has large stationary power consumption, its component has to be replaced to vary a voltage level, and the number of components is large. SOLUTION: The liquid crystal display device is provided with a setting register 100 where the amplitudes and voltage levels of the driving voltage of a common electrode and the non-scanning period voltage of scanning lines are set, an amplitude reference generating circuit 101 which generates an amplitude reference voltage for the driving voltage of the common electrode and the non-scanning period voltage of the scanning lines according to the set values, a VcomH reference generating circuit 102 and a VcomL generating circuit 100 which performs the AC driving of the common electrode to the amplitude and voltage level determined according to the amplitude reference voltage and set values, and a VgoffH generating circuit 104 and a VgoffL reference generating circuit 105 which generate the non-scanning period voltage of the scanning lines in phase with and to the same amplitude with the driving voltage of the common electrode with the amplitude and voltage level determined by the amplitude reference voltage and set values.

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