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1. 发明专利

JPH0660008A TWO-PORT MEMORY 失效
公开(公告)号：JPH0660008A
公开(公告)日：1994-03-04
申请号：JP21152592
申请日：1992-08-07
申请人： HITACHI CABLE
发明人： ASANO MITSUHARU , TANNO KAZUHIKO , HAYAMA HIROYUKI
IPC分类号： G06F13/362 , G06F12/00 , G06F13/18 , G06F13/38 , G11C11/401
摘要： PURPOSE:To obtain the two-port memory which is fast in access speed even when access requests from different ports are made at the same time by giving priority to a port which requesting access to an address in the same page with access by a port which is accepted preferentially to the access. CONSTITUTION:Page decision circuits 13a and 13b are connected to a memory control circuit 6 through a control signal line 14 so as to register the ROW address of the precedent access, and the page decision circuits 13a and 13b are connected to the memory control circuit 6 through signal lines 15a and 15b in order to inform the memory control circuit 6 of decision results. Then the OR result between the outputs of the page decision circuits 13a and 13b is outputted to the memory control circuit 6. Therefore, a page-out state can be suppressed by selecting the port which requests access to an address in the same page, so high-speed access is attained.

2. 发明专利

JPH0522326A LINE EXCHANGE TYPE LOOP NETWORK 失效
公开(公告)号：JPH0522326A
公开(公告)日：1993-01-29
申请号：JP17016591
申请日：1991-07-10
申请人： HITACHI CABLE
发明人： TANNO KAZUHIKO , HAYAMA HIROYUKI
IPC分类号： H04L12/42
摘要： PURPOSE:To reduce the redundant hardware as a whole even when plural standby LCS sets are provided in the line exchange type loop network. CONSTITUTION:A frame buffer is not mounted to an LCS 26, and standby LCS 1c, 1d in the line exchange type loop network and a frame buffer exclusive node station 8 is added in place of the buffer as one node station on the network.

3. 发明专利

JPH0553969A DMA CONTROL CIRCUIT 失效
公开(公告)号：JPH0553969A
公开(公告)日：1993-03-05
申请号：JP21212891
申请日：1991-08-23
申请人： HITACHI CABLE
发明人： ASANO MITSUHARU , SOAN HIDEO , HAYAMA HIROYUKI , TANNO KAZUHIKO
IPC分类号： G06F13/28
摘要： PURPOSE:To provide the DMA control circuit which can reduce an influence exerted upon the performance of a microprocessor and can transfer data at a high speed. CONSTITUTION:A DMA control circuit 2 is provided with a means to calculate average time for acquiring a bus from a microprocessor 1, the average time for acquiring buses 5-7 from the microprocessor 1 is calculated, and the relevant time is compared with time for continuously transferring data or for transferring data specified times. When the average time for acquiring the buses 5-7 from the microprocessor 1 is longer, time for acquiring the buses 5-7 and for continuously transferring time is increased and when the average time for acquiring the buses from the microprocessor 1 is shorter, time for acquiring the buses 5-7 and for continuously transferring data is decreased.

4. 发明专利

JPH066364A AUTOMATIC RECOGNITION METHOD FOR MOUNTED EXPANSION BOARD 失效
公开(公告)号：JPH066364A
公开(公告)日：1994-01-14
申请号：JP16300392
申请日：1992-06-22
申请人： HITACHI CABLE
发明人： TANNO KAZUHIKO , HAYAMA HIROYUKI , ASANO MITSUHARU , SOAN HIDEO
IPC分类号： G06F13/14 , H04L12/42 , H04Q3/42
摘要： PURPOSE:To allow a basic board to recognize automatically number of mounted expansion boards and its mounted position without manual operation or a decided specific mount. CONSTITUTION:A value received by an expansion board 2 through a transmission path 6 passing through all expansion boards 2 mounted and returning to the basic board 1 is sent while being incremented by a different value in response to a position of board inserted slot, the sum of incremented values of sets of optional boards is decided differently entirely and the values through the transmission path returned through circulation are detected by the basic board 1. Or in other embodiment, each expansion board 2 has a different delay time from the position of the board insertion slot and the sum of delay times of sets of optional expansion boards differs from each other and the delay time returned through all the expansion boards 2 is detected by the basic board 1.

5. 发明专利

JPH0573474A DMA CONTROL CIRCUIT 失效
公开(公告)号：JPH0573474A
公开(公告)日：1993-03-26
申请号：JP23485991
申请日：1991-09-13
申请人： HITACHI CABLE
发明人： ASANO MITSUHARU , HAYAMA HIROYUKI , SOAN HIDEO , TANNO KAZUHIKO
IPC分类号： G06F13/28
摘要： PURPOSE:To constitute the circuit so that the influence is scarcely exerted on the performance of a microprocessor, and also, data can be transferred at a high speed. CONSTITUTION:The DMA control circuit is provided with a means 26 for deciding whether a microprocessor 1 is using a bus or not, and with respect to time or the number of times of transferring continuously data during a time from acquiring the bus till releasing it, in the case it is decided that the microprocessor 1 is not using the bus at the time of acquiring the bus, the time and the number of times are increased every time the data is transferred continuously, and also, in the case it is decided that the microprocessor 1 is using the bus at the time of acquiring the bus, the time or the number of times of transferring continuously the data is decreased to the prescribed value, and thereafter, in the case it is decided that the microprocessor 1 is not using the bus at the time of acquiring the bus, the time or the number of times of transferring continuously the data is increased every time the data is transferred continuously.

6. 发明专利

JPH06175966A DATA TRANSFER SYSTEM 失效
公开(公告)号：JPH06175966A
公开(公告)日：1994-06-24
申请号：JP32535592
申请日：1992-12-04
申请人： HITACHI CABLE
发明人： TANNO KAZUHIKO , HAYAMA HIROYUKI , OGAWA TSUGIO , ASANO MITSUHARU , NITANI MICHIO
IPC分类号： G06F13/28
摘要： PURPOSE:To improve the access efficiency of a CPU by sending a DMA interruption report to a direct memory access DMA circuit from the CPU through an external access circuit thereby eliminating the wait time of an external access request from the CPU without degrading the DMA transfer performance. CONSTITUTION:A CPU 11 communicates with another module through an external access circuit 13, and a DMA circuit 12 transfers data to another module connected to a common bus 4 without passing the CPU 11. The DMA interruption report can be sent from the external access circuit 13 to the DMA circuit 12. Consequently, if the CPU 11 issues an access request to another module while the DMA circuit 12 transfers data to another module connected to the common bus 4 without passing the CPU 11, the DMA interruption report is sent to the external access circuit 13, and the DMA circuit 12 interrupts data transfer in accordance with this report while occupying the common bus 4. The DMA circuit 12 restarts data transfer just after the end of the access request of the CPU 11.

7. 发明专利

JPH05158864A DMA CONTROLLER 失效
公开(公告)号：JPH05158864A
公开(公告)日：1993-06-25
申请号：JP32468091
申请日：1991-12-09
申请人： HITACHI CABLE
发明人： HAYAMA HIROYUKI , ASANO MITSUHARU , SOAN HIDEO , TANNO KAZUHIKO
IPC分类号： G06F13/28
摘要： PURPOSE:To improve an efficiency by changing the rate of the operation of an MPU and the rate of the operation of a DMA according to the operation level of a microcomputer system. CONSTITUTION:The number of times of block transfer for interruption mask levels 0-7, are sequentially infinity , infinity , 24, 12, 8, 4, 0, 0. When the number of times of the block transfer is 0 at the interruption levels 7 and 6, a DMA data transfer is prohibited, and only an MPU 1 is operated. Conversely, when the number of times of the block transfer is infinity at the mask levels 1 and 0, a control is not returned to the MPU 1 until the entire prescribed transfer data are transferred once a DMA data transmission is started. At the mask levels 5-2, a DMA control circuit 3 obtains a bus 5, transfers the data only at the number of times of the block transfer, releases the bus, returns the control to the MPU 1, and transfers the prescribed data several times.

8. 发明专利

JPH05150863A AUTOMATIC RECOGNIZING METHOD FOR MOUNTING OF EXTENSION BOARD 失效
公开(公告)号：JPH05150863A
公开(公告)日：1993-06-18
申请号：JP31264691
申请日：1991-11-27
申请人： HITACHI CABLE
发明人： SOAN HIDEO , HAYAMA HIROYUKI , ASANO MITSUHARU , TANNO KAZUHIKO
IPC分类号： G06F1/18 , H04L12/28
摘要： PURPOSE:To provide a recognizing method that enables a basic board to automatically recognize the number of mounted extension boards with no intervention of a manual operation. CONSTITUTION:A single basic board 1 and plural extension boards 2a-2n are stored in the same housing. The number of extension boards is not fixed and can freely set. In such a constitution, the delay time when the test data sent from the board 1 onto a transmission path starting from the board 1 and returns to the board 1 through the boards 2a-2n are returned to the board 1 after passing through all boards 2a-2n or the total delay time of the boards 2a-2n is detected. So that the number of mounted extension boards can be recognized.

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