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1. 发明申请

WO2011025495A1 TWO TERMINAL MEMCAPACITOR DEVICE 审中-公开
标题翻译：两端终端设备
公开(公告)号：WO2011025495A1
公开(公告)日：2011-03-03
申请号：PCT/US2009/055401
申请日：2009-08-28
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PICKETT, Matthew, D. , BORGHETTI, Julien , YANG, Jianhua
发明人： PICKETT, Matthew, D. , BORGHETTI, Julien , YANG, Jianhua
IPC分类号： H01L27/04 , H01L27/115
CPC分类号： G11C11/24 , H01G7/06 , H01L27/101 , H01L28/40 , H01L29/167 , H01L29/93
摘要： A memcapacitor device (100) includes a memcapacitive matrix (115) interposed between a first electrode (105) and a second electrode (110). The memcapacitive matrix includes deep level dopants (225) having a first decay time constant and shallow level dopants (230) having a second decay time constant. The second decay time constant is substantially shorter than the first decay time constant. The capacitance (600) of the memcapacitor device (100) depends upon an initial voltage applied across the memcapacitive matrix (115) and a time dependent change in capacitance of the memcapacitor device (100) depends upon the first decay time constant. A method for forming a memcapacitive device is also provided.
摘要翻译：电容器装置（100）包括介于第一电极（105）和第二电极（110）之间的存储电容矩阵（115）。所述存储电容矩阵包括具有第一衰减时间常数的深层掺杂剂（225）和具有第二衰减时间常数的浅层掺杂剂（230）。第二衰减时间常数明显短于第一衰减时间常数。存储电容器装置（100）的电容（600）取决于施加在存储电容矩阵（115）上的初始电压，并且电容器装置（100）的时间相关的电容变化取决于第一衰减时间常数。还提供了一种形成电容器件的方法。

2. 发明申请

WO2010087836A1 ELECTRICALLY ACTUATED DEVICE 审中-公开
标题翻译：电动启动装置
公开(公告)号：WO2010087836A1
公开(公告)日：2010-08-05
申请号：PCT/US2009/032496
申请日：2009-01-29
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PICKETT, Matthew, D. , CHO, Hans, S. , BORGHETTI, Julien , STEWART, Duncan
发明人： PICKETT, Matthew, D. , CHO, Hans, S. , BORGHETTI, Julien , STEWART, Duncan
IPC分类号： H01L29/40 , H03K19/0948 , H03K17/687 , G06F13/00
CPC分类号： H01L45/145 , H01L27/2472 , H01L45/08 , H01L45/1233 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/165
摘要： An electrically actuated device includes a first electrode and a second electrode crossing the first electrode at a non-zero angle, thereby forming a junction therebetween. A material is established on the first electrode and at the junction. At least a portion of the material is a matrix region. A current conduction channel extends substantially vertically between the first and second electrodes, and is defined in at least a portion of the material positioned at the junction. The current conduction channel has a controlled profile of dopants therein.
摘要翻译：电驱动装置包括第一电极和第二电极，其以非零角度与第一电极交叉，从而在它们之间形成接合部。在第一电极和接合处建立材料。材料的至少一部分是矩阵区域。电流传导通道在第一和第二电极之间基本垂直地延伸，并且限定在位于结处的材料的至少一部分中。电流传导通道在其中具有受控的掺杂剂分布。

3. 发明申请

WO2011112197A1 DEVICE HAVING MEMRISTIVE MEMORY 审中-公开
标题翻译：具有记忆力的装置
公开(公告)号：WO2011112197A1
公开(公告)日：2011-09-15
申请号：PCT/US2010/027129
申请日：2010-03-12
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PICKETT, Matthew, D. , YANG, Jianhua , RIBEIRO, Gilberto, Medeiros
发明人： PICKETT, Matthew, D. , YANG, Jianhua , RIBEIRO, Gilberto, Medeiros
IPC分类号： H01L27/115 , H01L21/8247 , G11C16/00
CPC分类号： H01L27/0688 , G11C13/0002 , G11C13/0007 , G11C2213/71 , H01L27/101
摘要： A device (10) may include a semiconductor layer section (25) and a memory layer section (45) disposed above the semiconductor layer section (25). The semiconductor layer section (25) may include a processor (12; 412) and input/output block (16; 416), and the memory layer section (45) may include memristive memory (14; 300). A method of forming such device (10), and an apparatus (600) including such device (10) are also disclosed. Other embodiments are described and claimed.
摘要翻译：器件（10）可以包括设置在半导体层部分（25）上方的半导体层部分（25）和存储层部分（45）。半导体层部分（25）可以包括处理器（12; 412）和输入/输出块（16; 416），并且存储器层部分（45）可以包括忆阻存储器（14; 300）。还公开了形成这种装置（10）的方法，以及包括这种装置（10）的装置（600）。描述和要求保护其他实施例。

4. 发明申请

WO2011005266A1 MEMRISTIVE JUNCTION WITH INTRINSIC RECTIFIER 审中-公开
标题翻译：与内部整流器的结合接头
公开(公告)号：WO2011005266A1
公开(公告)日：2011-01-13
申请号：PCT/US2009/050277
申请日：2009-07-10
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , YANG, Jianhua , STRACHAN, John, Paul , PICKETT, Matthew, D.
发明人： YANG, Jianhua , STRACHAN, John, Paul , PICKETT, Matthew, D.
IPC分类号： H01L29/40 , H01L27/115
CPC分类号： H01L29/24 , G11C13/0007 , G11C13/003 , G11C2213/73 , H01L27/101 , H01L27/2463 , H01L29/8615 , H01L29/872 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/147
摘要： A memristive junction (400) can comprise a first electrode (102) and second electrode (104), with a memristive region (106) situated between them. The memristive region is configured to switch between two activation states via a switching voltage (118) applied between the electrodes. The activation state can be ascertained by application of a reading voltage between the first electrode and second electrode. The junction further comprises a rectifier region situated at an interface (420) between the first electrode and the memristive region, and comprising a layer (402) of temperature-responsive transition material that is substantially conductive at the switching voltage and substantially resistive at the reading voltage.
摘要翻译：忆阻接头（400）可以包括第一电极（102）和第二电极（104），其间具有位于它们之间的忆阻区（106）。忆阻区被配置为经由施加在电极之间的开关电压（118）在两个激活状态之间切换。可以通过在第一电极和第二电极之间施加读取电压来确定激活状态。连接点还包括位于第一电极和忆阻区域之间的界面（420）处的整流器区域，并且包括温度响应性过渡材料层（402），其在开关电压下基本上是导电的，并且在读数时基本上是电阻的电压。

5. 发明申请

WO2013062561A1 SHIFTABLE MEMORY SUPPORTING ATOMIC OPERATION 审中-公开
标题翻译：支持原子能操作的可移植记忆
公开(公告)号：WO2013062561A1
公开(公告)日：2013-05-02
申请号：PCT/US2011/058181
申请日：2011-10-27
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , GOLAB, Wojciech , PICKETT, Matthew, D. , KARP, Alan, H.
发明人： GOLAB, Wojciech , PICKETT, Matthew, D. , KARP, Alan, H.
IPC分类号： G11C19/00 , G06F12/00
CPC分类号： G11C7/1036 , G06F5/00 , G06F9/30032 , G06F9/30134 , G06F9/544 , G06F15/7821 , G06F2209/521 , G11C19/188 , G11C19/287
摘要： A shiftable memory supporting atomic operation employs built-in shifting capability to shift a contiguous subset of data from a first location to a second location within memory during an atomic operation. The shiftable memory includes the memory to store data. The memory has the built-in shifting capability. The shiftable memory further includes an atomic primitive defined on the memory to operate on the contiguous subset.
摘要翻译：支持原子操作的可移动存储器在原子操作期间使用内置的移位能力来将数据的连续子集从存储器中的第一位置移动到第二位置。可移动存储器包括用于存储数据的存储器。内存具有内置的移动功能。可移位存储器还包括在存储器上定义以在连续子集上操作的原子原语。

6. 发明申请

WO2013002772A1 SHIFTABLE MEMORY 审中-公开
公开(公告)号：WO2013002772A1
公开(公告)日：2013-01-03
申请号：PCT/US2011/042223
申请日：2011-06-28
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , KELLY, Terrence, P. , DAVIS, Alan, L. , PICKETT, Matthew, D.
发明人： KELLY, Terrence, P. , DAVIS, Alan, L. , PICKETT, Matthew, D.
IPC分类号： G11C19/00 , G11C11/413 , G06F12/00
CPC分类号： G11C7/1006 , G11C8/04 , G11C8/10 , G11C8/12 , G11C19/28 , G11C19/287
摘要： A shiftable memory is employed in a system and a method to shift a contiguous subset of stored data within the shiftable memory. The shiftable memory includes a memory having built-in shifting capability to shift a contiguous subset of data stored by the memory from a first location to a second location within the memory. The contiguous subset has a size that is smaller than a total size of the memory. The system further includes a processor to provide an address and the length of the contiguous subset. The method includes selecting the contiguous subset of data and shifting the selected contiguous subset.
摘要翻译：在可移动存储器中使用可移位存储器和用于移位存储数据的连续子集的方法。可移位存储器包括具有内置移位能力的存储器，用于将存储器存储的数据的连续子集从第一位置移动到存储器内的第二位置。连续子集的大小小于存储器的总大小。该系统还包括处理器，用于提供连续子集的地址和长度。该方法包括选择连续的数据子集并移动所选择的连续子集。

7. 发明申请

WO2013162594A1 SHIELDING A MEMORY DEVICE 审中-公开
标题翻译：屏蔽记忆设备
公开(公告)号：WO2013162594A1
公开(公告)日：2013-10-31
申请号：PCT/US2012/035440
申请日：2012-04-27
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , WARNER, Craig , GOSTIN, Gary , PICKETT, Matthew, D.
发明人： WARNER, Craig , GOSTIN, Gary , PICKETT, Matthew, D.
IPC分类号： G06F12/00 , G06F12/08 , G06F13/16
CPC分类号： G06F12/0833 , G06F12/0238 , G06F12/0866 , G06F12/122 , G06F13/1673 , G06F2212/1036 , G06F2212/312 , G06F2212/621 , G06F2212/7211
摘要： A method of shielding a memory device (110) from high write rates comprising receiving instructions to write data at a memory controller (105), the memory controller (105) comprising a cache (120) comprising a number of cache lines defining stored data, with the memory controller (105), updating a cache line in response to a write hit in the cache (120), and with the memory controller (105), executing the instruction to write data in response to a cache miss to a cache line within the cache (120) in which the memory controller (105) prioritizes for writing to the cache (120) over writing to the memory device (110).
摘要翻译：一种将存储器件（110）从高写入速率屏蔽的方法，包括接收在存储器控制器（105）上写入数据的指令，所述存储器控制器（105）包括高速缓存（120），所述高速缓存包括限定存储数据的多条高速缓存线，利用存储器控制器（105），响应于高速缓存（120）中的写命中，以及与存储器控制器（105）一起更新高速缓存行，响应于高速缓存未命中将数据写入高速缓存行在所述存储器控制器（105）通过写入所述存储器件（110）来优先处理写入高速缓存（120）的高速缓存（120）内。

8. 发明申请

WO2013115779A1 WORD SHIFT STATIC RANDOM ACCESS MEMORY (WS-SRAM) 审中-公开
标题翻译： WORD移动静态随机存取存储器（WS-SRAM）
公开(公告)号：WO2013115779A1
公开(公告)日：2013-08-08
申请号：PCT/US2012/023200
申请日：2012-01-30
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick, A. , PICKETT, Matthew, D.
发明人： PERNER, Frederick, A. , PICKETT, Matthew, D.
IPC分类号： G11C11/413
CPC分类号： G11C11/40615 , G11C11/407 , G11C11/412 , G11C19/28
摘要： Word shift static random access memory (WS-SRAM) cell, word shift static random access memory (WS-SRAM) and method using the same employ dynamic storage mode switching to shift data. The WS-SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, a dynamic/static (D/S) mode selector to selectably switch the WS-SRAM cell between the dynamic storage mode and a static storage mode, and a column selector to selectably determine whether or not the WS-SRAM cell accepts shifted data. The WS-SRAM includes a plurality of WS-SRAM cells arranged in an array and a controller to shift data. The method includes switching a storage mode and activating a column selector of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected WS-SRAM cell.
摘要翻译：字移位静态随机存取存储器（WS-SRAM）单元，字移动静态随机存取存储器（WS-SRAM）和使用该方法的方法采用动态存储模式切换来移位数据。 WS-SRAM单元包括具有一对交叉耦合元件以存储数据的静态随机存取存储器（SRAM）单元，动态/静态（D / S）模式选择器，用于可选择地在动态存储器之间切换WS-SRAM单元模式和静态存储模式，以及列选择器，可选地确定WS-SRAM单元是否接受移位数据。 WS-SRAM包括排列成阵列的多个WS-SRAM单元和用于移位数据的控制器。该方法包括切换存储模式并激活列数据选择器，将数据从相邻的存储器单元耦合到并将所耦合的数据存储在所选择的WS-SRAM单元中。

9. 发明申请

WO2012067660A1 METHOD AND CIRCUIT FOR SWITCHING A MEMRISTIVE DEVICE 审中-公开
标题翻译：用于切换物理装置的方法和电路
公开(公告)号：WO2012067660A1
公开(公告)日：2012-05-24
申请号：PCT/US2011/023250
申请日：2011-01-31
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick , YI, Wei , PICKETT, Matthew, D.
发明人： PERNER, Frederick , YI, Wei , PICKETT, Matthew, D.
IPC分类号： H03K17/30 , H01L29/41 , G11C11/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C2013/0066 , G11C2013/0073 , G11C2013/0078 , G11C2211/5624 , G11C2211/5645 , G11C2213/15
摘要： A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the current ramp is monitored. When the resistance of the memristive device reaches the target value, the current ramp is removed.
摘要翻译：一种切换忆阻器件的方法将所选极性的电流斜坡应用于忆阻器件。监测电流斜坡期间器件的电阻。当忆阻器的电阻达到目标值时，电流斜坡被去除。

10. 发明申请

WO2010144097A1 HIERARCHICAL ON-CHIP MEMORY 审中-公开
标题翻译：分层片上记忆
公开(公告)号：WO2010144097A1
公开(公告)日：2010-12-16
申请号：PCT/US2009/047253
申请日：2009-06-12
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , RIBEIRO, Gilberto, Medeiros , WILLIAMS, R., Stanley , PICKETT, Matthew, D.
发明人： RIBEIRO, Gilberto, Medeiros , WILLIAMS, R., Stanley , PICKETT, Matthew, D.
IPC分类号： H01L23/12 , G11C5/02
CPC分类号： G11C5/02 , G11C5/063 , G11C2213/71
摘要： A hierarchical on-chip memory (400) includes an area distributed CMOS layer (310) comprising input/output functionality and volatile memory and via array (325, 330), the area distributed CMOS layer (310) configured to selectively address the via array (325, 330). A crossbar memory (305) overlies the area distributed CMOS layer (310) and includes programmable crosspoint devices (315) which are uniquely accessed through the via array (325, 330). A method for utilizing hierarchical on-chip memory (400) includes storing frequently rewritten data in a volatile memory and storing data which is not frequently rewritten in a non-volatile memory (305), where the volatile memory is contained within an area distributed CMOS layer (310) and the non-volatile memory (305) is formed over and accessed through the area distributed CMOS layer (310).
摘要翻译：分层片上存储器（400）包括包括输入/输出功能的区域分布式CMOS层（310）和易失性存储器和通孔阵列（325,330），所述区域分布式CMOS层（310）被配置为选择性地寻址通孔阵列（325,330）。交叉开关存储器（305）覆盖区域分布式CMOS层（310），并且包括通过通孔阵列（325,330）唯一访问的可编程交叉点设备（315）。一种用于利用分层片上存储器（400）的方法包括：将经常重写的数据存储在易失性存储器中，并将非频繁重写的数据存储在非易失性存储器（305）中，其中易失性存储器包含在区域分布式CMOS 层（310）和非易失性存储器（305）形成在区域分布式CMOS层（310）上并通过区域分布式CMOS层（310）访问。

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