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1. 发明申请

WO2014011149A1 LIST SORT STATIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：列表静态随机存取存储器
公开(公告)号：WO2014011149A1
公开(公告)日：2014-01-16
申请号：PCT/US2012/046018
申请日：2012-07-10
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick A.
发明人： PERNER, Frederick A.
IPC分类号： G11C11/413
CPC分类号： G11C11/419 , G11C11/412 , G11C15/04 , G11C19/28
摘要： A list sort static random access memory (LSSRAM) unit cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data and a dynamic/static (D/S) mode selector to selectably switch the LSSRAM unit cell between a dynamic storage mode and a static storage mode. The LSSRAM unit cell further includes a swap selector to swap the stored data with data stored in an adjacent memory cell during the dynamic storage mode when the swap selector is activated, and a data comparator to compare the stored data in the SRAM cell with the data stored in the adjacent memory cell and to activate the swap selector according to a result of the comparison.
摘要翻译：列表排序静态随机存取存储器（LSSRAM）单元包括具有一对交叉耦合元件以存储数据的静态随机存取存储器（SRAM）单元和用于可选地切换LSSRAM的动态/静态（D / S）模式选择器动态存储模式和静态存储模式之间的单元格。所述LSSRAM单元还包括交换选择器，用于在所述交换选择器被激活时在所述动态存储模式期间与存储在相邻存储器单元中的数据交换所存储的数据;以及数据比较器，用于将所述SRAM单元中存储的数据与所述数据进行比较存储在相邻存储单元中并且根据比较的结果激活交换选择器。

2. 发明申请

WO2005022543A1 METHOD AND SYSTEM FOR CONTROLLING WRITE CURRENT IN MAGNETIC MEMORY 审中-公开
标题翻译：用于控制磁记忆中写入电流的方法和系统
公开(公告)号：WO2005022543A1
公开(公告)日：2005-03-10
申请号：PCT/US2004/026183
申请日：2004-08-11
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick, A. , SMITH, Kenneth, K.
发明人： PERNER, Frederick, A. , SMITH, Kenneth, K.
IPC分类号： G11C8/08
CPC分类号： G11C11/16 , G11C8/08
摘要： Methods and apparatuses are disclosed for controlling the write current in magnetic memory. In some embodiments, the method includes: providing a current in a plurality of memory write lines (32) (where write lines (30) may be magnetically coupled to at least one memory element (34)), coupling a first and second plurality of transistors (36,38) to either end of memory write line (32), and altering the conduction state of individual transistors within the first and second plurality of transistors (36,38).
摘要翻译：公开了用于控制磁存储器中的写入电流的方法和装置。在一些实施例中，该方法包括：在多个存储器写入线（32）中提供电流（其中写入线（30）可以磁耦合到至少一个存储器元件（34）），耦合第一和第二多个晶体管（36,38）到存储器写入线（32）的任一端，以及改变第一和第二多个晶体管（36,38）内的各个晶体管的导通状态。

3. 发明申请

WO2013115779A1 WORD SHIFT STATIC RANDOM ACCESS MEMORY (WS-SRAM) 审中-公开
标题翻译： WORD移动静态随机存取存储器（WS-SRAM）
公开(公告)号：WO2013115779A1
公开(公告)日：2013-08-08
申请号：PCT/US2012/023200
申请日：2012-01-30
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick, A. , PICKETT, Matthew, D.
发明人： PERNER, Frederick, A. , PICKETT, Matthew, D.
IPC分类号： G11C11/413
CPC分类号： G11C11/40615 , G11C11/407 , G11C11/412 , G11C19/28
摘要： Word shift static random access memory (WS-SRAM) cell, word shift static random access memory (WS-SRAM) and method using the same employ dynamic storage mode switching to shift data. The WS-SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, a dynamic/static (D/S) mode selector to selectably switch the WS-SRAM cell between the dynamic storage mode and a static storage mode, and a column selector to selectably determine whether or not the WS-SRAM cell accepts shifted data. The WS-SRAM includes a plurality of WS-SRAM cells arranged in an array and a controller to shift data. The method includes switching a storage mode and activating a column selector of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected WS-SRAM cell.
摘要翻译：字移位静态随机存取存储器（WS-SRAM）单元，字移动静态随机存取存储器（WS-SRAM）和使用该方法的方法采用动态存储模式切换来移位数据。 WS-SRAM单元包括具有一对交叉耦合元件以存储数据的静态随机存取存储器（SRAM）单元，动态/静态（D / S）模式选择器，用于可选择地在动态存储器之间切换WS-SRAM单元模式和静态存储模式，以及列选择器，可选地确定WS-SRAM单元是否接受移位数据。 WS-SRAM包括排列成阵列的多个WS-SRAM单元和用于移位数据的控制器。该方法包括切换存储模式并激活列数据选择器，将数据从相邻的存储器单元耦合到并将所耦合的数据存储在所选择的WS-SRAM单元中。

4. 发明申请

WO2006041430A1 DATA STORAGE DEVICE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：数据存储装置及其形成方法
公开(公告)号：WO2006041430A1
公开(公告)日：2006-04-20
申请号：PCT/US2004/030593
申请日：2004-09-17
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick A. , VAN BROCKLIN, Andrew L. , JACKSON, Warren B.
发明人： PERNER, Frederick A. , VAN BROCKLIN, Andrew L. , JACKSON, Warren B.
IPC分类号： G11C11/16
CPC分类号： G11C8/14 , G11C11/16 , G11C2213/72 , H01L27/224
摘要： A resistive cross point memory cell array comprising a plurality of word lines (14), a plurality of bit lines (16), a plurality of cross points formed by the word lines (14) and the bit lines (16), and a plurality of memory cells (18), each of the memory cells (18) being located at a different one of the cross points, wherein a first bit line (16) comprises a distributed series diode along an entire length of the bit line (16) such that each of the associated memory cells (18) located along the first bit line (16) is coupled between the distributed series diode and an associated word line (14).
摘要翻译：一种电阻交叉点存储单元阵列，包括多个字线（14），多个位线（16），由字线（14）和位线（16）形成的多个交叉点，以及多个的存储器单元（18）中，每个存储器单元（18）位于交叉点的不同的一个处，其中第一位线（16）包括沿着位线（16）的整个长度的分布式串联二极管，使得沿着第一位线（16）定位的每个相关联的存储器单元（18）耦合在分布式串联二极管和相关联的字线（14）之间。

5. 发明申请

WO2006009837A3 IRIS FEATURE DETECTION AND SENSOR-BASED EDGE DETECTION 审中-公开
标题翻译： IRIS特征检测和基于传感器的边缘检测
公开(公告)号：WO2006009837A3
公开(公告)日：2006-03-09
申请号：PCT/US2005021450
申请日：2005-06-17
申请人： HEWLETT PACKARD DEVELOPMENT CO , PERNER FREDERICK A
发明人： PERNER FREDERICK A
IPC分类号： A61B3/113 , A61B3/12 , A61B5/117 , G06K9/00
CPC分类号： G06K9/00597 , A61B3/1216 , A61B5/117 , A61B5/1171
摘要： An iris feature detector (110) includes a reflexive eye movement source (112-1124); a multiple image sensor (118); a controller (120), and a processor (122). The controller (120) causes the eye movement source (112-114) to cause rapid eye motion, and the sensor (118) to capture first and second iris images over a time interval in which only an iris can move in the first and second images. The processor (122) determines differences between the first and second images. The sensor (118) may be integrated with the processor (122). The integrated sensor/processor is not limited to iris feature detection, and may be used for edge detection for machine vision and other applications.
摘要翻译：虹膜特征检测器（110）包括反射性眼球运动源（112-1124）; 多图像传感器（118）; 控制器（120）和处理器（122）。控制器（120）使得眼睛运动源（112-114）引起快速眼睛运动，并且传感器（118）在一段时间间隔内捕获第一和第二虹膜图像，其中只有虹膜能够在第一和第二图片。处理器（122）确定第一和第二图像之间的差异。传感器（118）可以与处理器（122）集成。集成的传感器/处理器不限于虹膜特征检测，并且可用于机器视觉和其他应用的边缘检测。

6. 发明申请

WO2005106889A1 TWO CONDUCTOR THERMALLY ASSISTED MAGNETIC MEMORY 审中-公开
标题翻译：两个导体热辅助磁记忆
公开(公告)号：WO2005106889A1
公开(公告)日：2005-11-10
申请号：PCT/US2005/014232
申请日：2005-04-26
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY L.P. , PERNER, Frederick A. , WALMSLEY, Robert C , TRAN, Lung T.
发明人： PERNER, Frederick A. , WALMSLEY, Robert C , TRAN, Lung T.
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C11/1675
摘要： A method of performing a thermally assisted write operation on a selected two conductor spin valve memory (SVM) cell 202 having a material wherein the coercivity is decreased upon an increase in temperature. In a particular embodiment, a first write magnetic field 500 is established by a first write current 360 flowing from a first voltage potential to a second voltage potential as applied to the first conductor 204. A second write magnetic field 502 is established by a second write current 362 flowing from a third voltage potential to a fourth voltage potential as applied to the second conductor 206. The voltage potential of the first conductor 204 is greater than the voltage potential of the second conductor 206. As a result, a third current 364, flows from the first conductor 204 through the SVM cell 202 to the second conductor 206. The SVM cell 202 has an internal resistance such that the flowing current 364 generates heat 366 within the SVM cell 202. As the SVM cell 202 is self heated, the coercivity of the SVM cell 202 falls below the combined write magnetic fields 500, 502.
摘要翻译：对具有材料的选定的两个导体自旋阀存储器（SVM）单元202执行热辅助写入操作的方法，其中矫顽力在温度升高时降低。在特定实施例中，通过施加到第一导体204上的从第一电压电位流向第二电压电位的第一写入电流360建立第一写入磁场500.第二写入磁场502通过第二写入电流362从施加到第二导体206的第三电压电位流向第四电压电位。第一导体204的电压电位大于第二导体206的电压电位。结果，第三电流364，从第一导体204通过SVM单元202流向第二导体206. SVM单元202具有内部电阻，使得流动电流364在SVM单元202内产生热量366.由于SVM单元202是自加热的， SVM单元202的矫顽力低于组合写入磁场500,502。

7. 发明申请

WO2013115778A1 DYNAMIC/STATIC RANDOM ACCESS MEMORY (D/SRAM) 审中-公开
标题翻译：动态/静态随机存取存储器（D / SRAM）
公开(公告)号：WO2013115778A1
公开(公告)日：2013-08-08
申请号：PCT/US2012/023197
申请日：2012-01-30
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick, A.
发明人： PERNER, Frederick, A.
IPC分类号： G11C7/10 , G11C11/40 , G11C11/41
CPC分类号： G11C11/407 , G11C11/412 , G11C11/417 , G11C19/00 , G11C19/28
摘要： Dynamic/static random access memory (D/SRAM) cell, block shift static random access memory (BS-SRAM) and method using the same employ dynamic storage mode and dynamic storage mode switching to shift data. The D/SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, and a dynamic/static (D/S) mode selector to selectably switch the D/SRAM cell between the dynamic storage mode and a static storage mode. The BS-SRAM includes a plurality of D/SRAM cells arranged in an array and a controller to shift data from an adjacent D/SRAM cell in a second row of the array to a D/SRAM cell in a first row. The method includes switching the mode of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected D/SRAM cell.
摘要翻译：动态/静态随机存取存储器（D / SRAM）单元，块移动静态随机存取存储器（BS-SRAM）和使用该方法的方法采用动态存储模式和动态存储模式切换来移位数据。 D / SRAM单元包括具有用于存储数据的一对交叉耦合元件的静态随机存取存储器（SRAM）单元，以及动态/静态（D / S）模式选择器，用于可选择地在D / 存储模式和静态存储模式。 BS-SRAM包括以阵列布置的多个D / SRAM单元和控制器，用于将数据从阵列的第二行中的相邻D / SRAM单元移位到第一行中的D / SRAM单元。该方法包括将来自相邻存储器单元的数据的耦合模式切换到所选择的D / SRAM单元中并将所耦合的数据存储在所选择的D / SRAM单元中。

8. 发明申请

WO2006115968A3 ACTIVE INTERCONNECTS AND CONTROL POINTS IN INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路中的主动互连和控制点
公开(公告)号：WO2006115968A3
公开(公告)日：2007-08-16
申请号：PCT/US2006014856
申请日：2006-04-19
申请人： HEWLETT PACKARD DEVELOPMENT CO , WILLIAMS R STANLEY , KUEKES PHILLIP J , PERNER FREDERICK A , SNIDER GREGORY S , STEWART DUNCAN
发明人： WILLIAMS R STANLEY , KUEKES PHILLIP J , PERNER FREDERICK A , SNIDER GREGORY S , STEWART DUNCAN
IPC分类号： H01L21/66
CPC分类号： H05K7/1092 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In various embodiments of the present invention, tunable resistors (1102) are introduced at the interconnect layer of the integrated circuits (102) in order to provide a means for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronics characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors (1102) included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains. In some cases, components and modules may be turned off, while, in other cases, components and modules may be turned on.
摘要翻译：在本发明的各种实施例中，可调谐电阻器（1102）被引入集成电路（102）的互连层，以便提供用于调整集成电路内的内部电压和/或电流水平以修复有缺陷的部件或配置后续制造的集成电路。例如，当某些内部组件（例如晶体管）由于制造缺陷而没有指定的电子特性时，根据本发明的实施例调整包括在集成电路的互连层中的可调电阻器（1102）的可变电阻可以用于调整内部电压和/或电平，以改善有缺陷的部件。在其他情况下，可调谐电阻器可以用作开关以配置集成电路部件，包括单独的晶体管和逻辑门以及更大的分层结构的功能模块和域。在某些情况下，可能会关闭组件和模块，而在其他情况下，可能会打开组件和模块。

9. 发明申请

WO2006115968A2 ACTIVE INTERCONNECTS AND CONTROL POINTS IN INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路中的主动互连和控制点
公开(公告)号：WO2006115968A2
公开(公告)日：2006-11-02
申请号：PCT/US2006/014856
申请日：2006-04-19
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , WILLIAMS, R., Stanley , KUEKES, Phillip, J. , PERNER, Frederick, A. , SNIDER, Gregory, S. , STEWART, Duncan
发明人： WILLIAMS, R., Stanley , KUEKES, Phillip, J. , PERNER, Frederick, A. , SNIDER, Gregory, S. , STEWART, Duncan
IPC分类号： H01L21/66
CPC分类号： H05K7/1092 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In various embodiments of the present invention, tunable resistors (1102) are introduced at the interconnect layer of the integrated circuits (102) in order to provide a means for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronics characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors (1102) included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains. In some cases, components and modules may be turned off, while, in other cases, components and modules may be turned on.
摘要翻译：在本发明的各种实施例中，可调谐电阻器（1102）被引入集成电路（102）的互连层，以便提供用于调整集成电路内的内部电压和/或电流水平以修复有缺陷的部件或配置后续制造的集成电路。例如，当诸如晶体管的某些内部部件由于制造缺陷而没有指定的电子特性时，根据本发明的实施例调整包括在集成电路的互连层中的可调电阻器（1102）的可变电阻可以用于调整内部电压和/或电平，以改善有缺陷的部件。在其他情况下，可调谐电阻器可以用作开关来配置集成电路组件，包括单独的晶体管和逻辑门以及更大的分层结构的功能模块和域。在某些情况下，可能会关闭组件和模块，而在其他情况下，可能会打开组件和模块。

10. 发明申请

WO2006009837A2 IRIS FEATURE DETECTION AND SENSOR-BASED EDGE DETECTION 审中-公开
标题翻译： IRIS特征检测和基于传感器的边缘检测
公开(公告)号：WO2006009837A2
公开(公告)日：2006-01-26
申请号：PCT/US2005/021450
申请日：2005-06-17
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY L.P. , PERNER, Frederick, A.
发明人： PERNER, Frederick, A.
IPC分类号： G06K9/00
CPC分类号： G06K9/00597 , A61B3/1216 , A61B5/117 , A61B5/1171
摘要： An iris feature detector (110) includes a reflexive eye movement source (112-1124); a multiple image sensor (118); a controller (120), and a processor (122). The controller (120) causes the eye movement source (112-114) to cause rapid eye motion, and the sensor (118) to capture first and second iris images over a time interval in which only an iris can move in the first and second images. The processor (122) determines differences between the first and second images. The sensor (118) may be integrated with the processor (122). The integrated sensor/processor is not limited to iris feature detection, and may be used for edge detection for machine vision and other applications.
摘要翻译：虹膜特征检测器（110）包括反射眼睛运动源（112-1124）; 多图像传感器（118）; 控制器（120）和处理器（122）。控制器（120）使得眼睛运动源（112-114）引起快速的眼睛运动，并且传感器（118）在仅一个虹膜可以在第一和第二眼睛中移动的时间间隔内捕获第一和第二光圈图像图片。处理器（122）确定第一和第二图像之间的差异。传感器（118）可以与处理器（122）集成。集成传感器/处理器不限于虹膜特征检测，可用于机器视觉和其他应用的边缘检测。

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