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    • 2. 发明申请
    • ARRAY OF NANOSCOPIC MOSFET TRANSISTORS AND FABRICATION METHODS
    • 纳米MOSFET晶体管阵列和制造方法
    • WO2005010981A2
    • 2005-02-03
    • PCT/US2004/020675
    • 2004-06-25
    • HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.GHOZEIL, Adam, L.STASIAK, JamesPETERS, Kevin, F.KAWAMOTO, Galen, H.
    • GHOZEIL, Adam, L.STASIAK, JamesPETERS, Kevin, F.KAWAMOTO, Galen, H.
    • H01L21/8234
    • H01L29/66825H01L21/28273H01L21/823437H01L29/1033H01L29/66575
    • A nanoscopic transistor (20) is made by forming an oxide layer on a semiconductor substrate (S10, S20), applying resist (S30), patterning the resist using imprint lithography to form a pattern aligned along a first direction (S40), applying a first ion-masking material over the pattern (S50), selectively lifting it off to leave a first ion mask to form a gate (S60), forming doped regions by implanting a suitable dopant (S70), applying another layer of resist (S90) and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction (S100), applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern (S120), and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask (S130). The method may be used to make an array (10 or 15) of nanoscopic transistors (20).
    • 通过在半导体衬底上形成氧化层(S10,S20),涂敷抗蚀剂(S30),使用压印光刻对抗蚀剂进行构图以形成沿着第一方向排列的图案(S40),制成纳米级晶体管(20) (S50),选择性地将其离开离开第一离子掩模以形成栅极(S60),通过注入合适的掺杂剂形成掺杂区域(S70),施加另一层抗蚀剂(S90) 以及使用压印光刻对所述第二抗蚀剂层进行构图以形成沿着第二方向对准的第二图案(S100),在所述第二图案上施加第二离子掩模材料,选择性地将其提起以离开由所述第二图案限定的第二离子掩模 (S120),并且通过根据第二离子掩模选择性地注入合适的第二掺杂剂而在衬底中形成第二掺杂区域(S130)。 该方法可用于制造纳米级晶体管(20)的阵列(10或15)。