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1. 发明授权

US06675182B1 Method and apparatus for performing rotate operations using cascaded multiplexers 失效
标题翻译：使用级联多路复用器执行旋转操作的方法和装置
公开(公告)号：US06675182B1
公开(公告)日：2004-01-06
申请号：US09649446
申请日：2000-08-25
申请人： H. Peter Hofstee , Hung C. Ngo , Kevin J. Nowka , Jun Sawada
发明人： H. Peter Hofstee , Hung C. Ngo , Kevin J. Nowka , Jun Sawada
IPC分类号： G06F1500
CPC分类号： G06F7/762 , G06F5/015
摘要： A method and apparatus performing rotate operations using cascaded multiplexers provides a scalable rotator circuit having a sub-field rotate capability that requires no additional interconnects at the sub-field endpoints. The rotator performs bit field swap operations at each stage of a series of cascaded multiplexers. The bit field size increases monotonically from a single bit to half of the rotator operand size. The control logic selects swap operations for each individual bit field at each stage, in order to arrange a desired rotated output vector.
摘要翻译：使用级联多路复用器执行旋转操作的方法和装置提供具有子场旋转能力的可缩放旋转电路，其不需要在子场端点处的附加互连。旋转器在一系列级联多路复用器的每个阶段执行位域交换操作。位域大小从单个位单调增加到旋转器操作数大小的一半。控制逻辑为每个级别的每个单独位字段选择交换操作，以便布置期望的旋转输出向量。

2. 发明授权

US08285765B2 System and method for implementing simplified arithmetic logic unit processing of value-based control dependence sequences 有权
标题翻译：用于实现基于价值的控制依赖序列的简化算术逻辑单元处理的系统和方法
公开(公告)号：US08285765B2
公开(公告)日：2012-10-09
申请号：US11608907
申请日：2006-12-11
申请人： Lei Chen , Hung C. Ngo , Kevin J. Nowka
发明人： Lei Chen , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G06F7/38
CPC分类号： G06F9/3885 , G06F7/575 , G06F9/30021 , G06F9/30094 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3857
摘要： A system and method for implementing arithmetic logic unit (ALU) support for value-based control dependence sequences. According to a first embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the ALU updates a storage location with a third value, which is the larger value. According to a second embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the ALU updates a storage location with a third value. The third value is a fourth value, if the carry-out signal designates the first value as the larger value or the third value is a fifth value, if the carry-out signal designates the second value as the larger value.
摘要翻译：用于实现算术逻辑单元（ALU）的系统和方法支持基于值的控制依赖序列。根据本发明的第一实施例，ALU产生指定第一和第二值中的一个作为较大值的进位输出信号。响应于进位信号，ALU用第三个值更新存储位置，该值是较大的值。根据本发明的第二实施例，ALU产生指定第一和第二值中的一个作为较大值的进位信号。响应于进位信号，ALU用第三个值更新存储位置。如果进位信号指定第二值作为较大值，则第三值是第四值，如果进位信号指定第一值作为较大值或第三值是第五值。

3. 发明授权

US07129754B2 Controlled load limited switch dynamic logic circuitry 失效
标题翻译：受控负载限制开关动态逻辑电路
公开(公告)号：US07129754B2
公开(公告)日：2006-10-31
申请号：US11082805
申请日：2005-03-17
申请人： Hung C. Ngo , Jayakumaran Sivagnaname , Kevin J. Nowka , Robert K. Montoye
发明人： Hung C. Ngo , Jayakumaran Sivagnaname , Kevin J. Nowka , Robert K. Montoye
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one when the circuit is in standby mode. The pre-charge device holds the dynamic node at a pre-charged logic one state independent of the clock. During the logic one evaluate time of the clock, the logic tree determines the asserted state of the dynamic node. During the evaluate time, the asserted state is latched by the static LSDL section. The dynamic node then re-charges to the pre-charge state. Since the pre-charge device is not de-gated during the evaluate time, the dynamic node cannot be inadvertently discharged by noise causing an error. Likewise, since the clock does not couple to the pre-charge device a load is removed from the clock tree lowering clock power.
摘要翻译：只要电路处于活动模式，LSDL电路用动态节点的预充电装置的正常时钟控制替代逻辑零的控制信号，并且当电路处于待机模式时，逻辑为逻辑1。预充电装置将动态节点保持在与时钟无关的预充电逻辑1状态。在逻辑1期间评估时钟的时间，逻辑树确定动态节点的被断言状态。在评估时间期间，断言状态由静态LSDL部分锁存。然后动态节点重新充电到预充电状态。由于在评估时间期间预充电装置没有被去门，所以动态节点不能被无意中的噪声放电，导致错误。类似地，由于时钟不耦合到预充电装置，所以从时钟树中降低时钟功率的负载被去除。

4. 发明授权

US06975134B2 Buffer/driver circuits 失效
标题翻译：缓冲/驱动电路
公开(公告)号：US06975134B2
公开(公告)日：2005-12-13
申请号：US10821048
申请日：2004-04-08
申请人： Jente B. Kuang , Hung C. Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03K17/16 , H03K19/00 , H03K19/003 , H03K19/017
CPC分类号： H03K19/00361 , H03K19/0016 , H03K19/01721
摘要： A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer/driver without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer/driver may be an inverter, non-inverter, or provide a multiple input logic function.
摘要翻译：具有用于驱动多个负载的大输出装置的缓冲器/驱动器配置有三个并行路径。第一个逻辑路径由小型设备组成，并配置为提供缓冲器/驱动器的逻辑功能，而无需驱动大负载。第二和第三逻辑路径具有直到上一个反相级的第一逻辑路径的逻辑功能。每个路径中的最后一个反相级是用于驱动缓冲区输出逻辑状态的单个器件。第二和第三逻辑路径具有电源门控，允许上拉和下拉器件的输入漂移去除栅极泄漏电压应力。当第二和第三逻辑路径是电源门控时，第一逻辑路径提供保持器功能以保持缓冲器输出的逻辑状态。缓冲器/驱动器可以是逆变器，非逆变器，或提供多输入逻辑功能。

5. 发明申请

US20080141046A1 PARTIAL DATA FLOW FUNCTIONAL GATING USING STRUCTURAL OR PARTIAL OPERAND VALUE INFORMATION 审中-公开
标题翻译：使用结构或部分操作价值信息的部分数据流功能评估
公开(公告)号：US20080141046A1
公开(公告)日：2008-06-12
申请号：US11567395
申请日：2006-12-06
申请人： Lei Chen , Jente B. Kuang , Brian R. Mestan , Hung C. Ngo , Kevin J. Nowka
发明人： Lei Chen , Jente B. Kuang , Brian R. Mestan , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F9/30014 , G06F9/30105 , G06F9/30112
摘要： The present invention relates to a methodology for controlling the power consumption in a computing device based upon extended register file extension values, the method further comprising the steps of identifying an upper bit data register value and a lower bit data register value for a data register value, and inputting the upper bit data register value to a detect logic component, wherein the upper bit data register value is used to generate a data register extension value. The method further comprises the steps of utilizing the data register extension value as a power control signal serving to activate or deactivate a power supply signal to a segment of a data path, and updating the data register extension value in a subsequent data register write computational function.
摘要翻译：本发明涉及一种用于基于扩展寄存器文件扩展值来控制计算设备中的功耗的方法，所述方法还包括以下步骤：识别数据寄存器值的高位数据寄存器值和低位数据寄存器值，并将高位数据寄存器值输入到检测逻辑分量，其中高位数据寄存器值用于产生数据寄存器扩展值。该方法还包括以下步骤：利用数据寄存器扩展值作为用于激活或去激活到数据路径的段的电源信号的功率控制信号，以及在随后的数据寄存器写入计算功能中更新数据寄存器扩展值。

6. 发明授权

US07298176B2 Dual-gate dynamic logic circuit with pre-charge keeper 有权
标题翻译：双栅极动态逻辑电路，带有预充电保护器
公开(公告)号：US07298176B2
公开(公告)日：2007-11-20
申请号：US11204401
申请日：2005-08-16
申请人： Hung C. Ngo , Ching-Te Chuang , Keunwoo Kim , Jente B. Kuang , Kevin J. Nowka
发明人： Hung C. Ngo , Ching-Te Chuang , Keunwoo Kim , Jente B. Kuang , Kevin J. Nowka
IPC分类号： H03K19/20
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.
摘要翻译：动态逻辑门具有非对称双栅极PFET器件，用于在时钟的预充电阶段期间对动态节点进行充电。逻辑树在时钟的评估阶段评估动态节点。非对称双栅极PFET器件的前栅极耦合到时钟信号，而后栅极耦合到电源的地电位。当时钟为逻辑0时，前门和后门都被偏置为ON，动态节点以最大电流充电。在时钟关断前门的评估阶段，时钟信号转变为逻辑1。背栅保持接通，并且非对称双栅极PFET器件作为具有足以抵抗动态节点上的泄漏的电流水平的保持器器件工作。

7. 发明授权

US07266707B2 Dynamic leakage control circuit 失效
标题翻译：动态泄漏控制电路
公开(公告)号：US07266707B2
公开(公告)日：2007-09-04
申请号：US10942419
申请日：2004-09-16
申请人： Hung C. Ngo , Jente B. Kuang , Kevin J. Nowka , Rajiv V. Joshi
发明人： Hung C. Ngo , Jente B. Kuang , Kevin J. Nowka , Rajiv V. Joshi
IPC分类号： G06F1/00
CPC分类号： G06F1/3228
摘要： A low power consumption pipeline circuit architecture has power partitioned pipeline stages. The first pipeline stage is non-power-gated for fast response in processing input data after receipt of a valid data signal. A power-gated second pipeline stage has two power-gated modes. Normally the power rail in the power-gated second pipeline stage is charged to a first voltage potential of a pipeline power supply. In the first power gated mode, the power rail is charged to a threshold voltage below the first voltage potential to reduce leakage. In the second power gated mode, the power rail is decoupled from the first voltage potential. A power-gated third pipeline stage has its power rail either coupled to the first voltage potential or power-gated where its power rail is decoupled from the first voltage potential. The power rail of the second power-gated pipeline stage charges to the first voltage potential before the third power-gated pipeline stage.
摘要翻译：低功耗流水线电路架构具有电源分配管线级。第一个流水线阶段是非功率门控，用于在接收到有效的数据信号后处理输入数据的快速响应。电源门控第二管道级具有两个电源门控模式。通常，电源门控第二管线级中的电源轨被充电到管线电源的第一电压电位。在第一电源门控模式中，电力轨被充电到低于第一电压电位的阈值电压以减少泄漏。在第二电源门控模式下，电源轨与第一电压电位分离。电源门控第三管线级具有其电源轨或者耦合到第一电压电势或电源门控，其电源轨与第一电压电势分离。第二电力门控管道阶段的电力轨道在第三电力门控管道阶段之前充电到第一电压电位。

8. 发明授权

US08555119B2 Test structure for characterizing multi-port static random access memory and register file arrays 失效
标题翻译：用于表征多端口静态随机存取存储器和寄存器文件阵列的测试结构
公开(公告)号：US08555119B2
公开(公告)日：2013-10-08
申请号：US13459932
申请日：2012-04-30
申请人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
发明人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G11C29/00
CPC分类号： G11C8/16 , G11C29/32 , G11C29/50 , G11C29/50012
摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.
摘要翻译：用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

9. 发明授权

US08261138B2 Test structure for characterizing multi-port static random access memory and register file arrays 有权
标题翻译：用于表征多端口静态随机存取存储器和寄存器文件阵列的测试结构
公开(公告)号：US08261138B2
公开(公告)日：2012-09-04
申请号：US11552158
申请日：2006-10-24
申请人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
发明人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G11C29/00
CPC分类号： G11C8/16 , G11C29/32 , G11C29/50 , G11C29/50012
摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.
摘要翻译：用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

10. 发明授权

US07760565B2 Wordline-to-bitline output timing ring oscillator circuit for evaluating storage array performance 失效
标题翻译：用于评估存储阵列性能的字线到位线输出定时环形振荡器电路
公开(公告)号：US07760565B2
公开(公告)日：2010-07-20
申请号：US11781994
申请日：2007-07-24
申请人： Jente B. Kuang , Jerry C. Kao , Hung C. Ngo , Kevin J. Nowka , Liang-Teck Pang , Jayakumaran Sivagnaname
发明人： Jente B. Kuang , Jerry C. Kao , Hung C. Ngo , Kevin J. Nowka , Liang-Teck Pang , Jayakumaran Sivagnaname
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/50 , G01R31/31937 , G11C29/50012 , G11C2029/1202 , G11C2029/1204
摘要： A wordline-to-bitline timing ring oscillator circuit for evaluating storage cell access time provides data on internal bitline access timing, and in particular the total wordline select-to-bitline read output timing. Columns of a storage array are connected in a ring, forming a ring oscillator. The bitline read circuit output of each column is connected to a wordline select input of a next column, with a net inversion around the ring, so that a ring oscillator is formed. The period of oscillation of the ring oscillator is determined by the total wordline select-to-bitline read circuit output timing for a first phase and the pre-charge interval time for the other phase, with the bitline read timing dominating. The circuit may be applied both to small-signal storage arrays, with the sense amplifier timing included within the ring oscillator period, or to large-signal storage arrays, with the read evaluate circuit timing included.
摘要翻译：用于评估存储单元访问时间的字线到位线定时环形振荡器电路提供关于内部位线访问定时的数据，特别是总字线选择到位线读出输出定时。存储阵列的列以环形连接，形成环形振荡器。每列的位线读取电路输出连接到下一列的字线选择输入，环绕环反转，从而形成环形振荡器。环形振荡器的振荡周期由第一相的总字线选择到位线读取电路输出定时和另一相的预充电间隔时间决定，而位线读取时序主导。该电路可以应用于小信号存储阵列，其中包括在环形振荡器周期内的读出放大器定时，或者包括读取评估电路时序的大信号存储阵列。

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