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1. 发明授权

US07351622B2 Methods of forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US07351622B2
公开(公告)日：2008-04-01
申请号：US11490613
申请日：2006-07-21
申请人： Gyoung-Ho Buh , Chang-Woo Ryoo , Yu-Gyun Shin , Tai-Su Park , Jin-Wook Lee
发明人： Gyoung-Ho Buh , Chang-Woo Ryoo , Yu-Gyun Shin , Tai-Su Park , Jin-Wook Lee
IPC分类号： H01L21/84 , H01L21/8234 , H01L21/336 , H01L21/00
CPC分类号： H01L29/7851 , H01L29/42392 , H01L29/66795 , H01L29/66803
摘要： A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type impurity elements, and the second source gas includes a dilution element regardless of the electrical characteristic of a doped region.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成由半导体形成的三维结构，并且通过使用第一源气体和第二源气体进行等离子体掺杂工艺，对三维结构进行各向同性地掺杂。第一源气体包括n型或p型杂质元素，第二源气体包括稀释元件，而与掺杂区域的电特性无关。

2. 发明申请

US20070020827A1 Methods of forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US20070020827A1
公开(公告)日：2007-01-25
申请号：US11490613
申请日：2006-07-21
申请人： Gyoung-Ho Buh , Chang-Woo Ryoo , Yu-Gyun Shin , Tai-Su Park , Jin-Wook Lee
发明人： Gyoung-Ho Buh , Chang-Woo Ryoo , Yu-Gyun Shin , Tai-Su Park , Jin-Wook Lee
IPC分类号： H01L21/84 , H01L21/8234 , H01L21/336 , H01L21/00
CPC分类号： H01L29/7851 , H01L29/42392 , H01L29/66795 , H01L29/66803
摘要： A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type impurity elements, and the second source gas includes a dilution element regardless of the electrical characteristic of a doped region.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成由半导体形成的三维结构，并且通过使用第一源气体和第二源气体进行等离子体掺杂工艺，对三维结构进行各向同性地掺杂。第一源气体包括n型或p型杂质元素，第二源气体包括稀释元件，而与掺杂区域的电特性无关。

3. 发明申请

US20060138478A1 Semiconductor device and method of forming same 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20060138478A1
公开(公告)日：2006-06-29
申请号：US11318827
申请日：2005-12-27
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Chang-Woo Ryoo , Soo-Jin Hong , Jin-Wook Lee , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Chang-Woo Ryoo , Soo-Jin Hong , Jin-Wook Lee , Guk-Hyon Yon
IPC分类号： H01L29/76 , H01L29/788 , H01L29/94
CPC分类号： H01L21/26506 , H01L29/40114 , H01L29/40117 , H01L29/6659 , H01L29/66825 , H01L29/66833 , H01L29/78 , H01L29/7833 , H01L29/7881
摘要： A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a gate spacer disposed on both sidewalls of the gate pattern, and a fixed charge layer disposed in the semiconductor substrate below the gate spacer. Elements generating fixed charges are injected into the fixed charge layer. A layer in which carriers induced by the fixed charge layer are accumulated is disposed below the fixed charge layer. The elements are segregated to a substrate of the semiconductor substrate from the inside of the semiconductor substrate by heat.
摘要翻译：半导体器件包括设置在半导体衬底上的栅极图案，设置在栅极图案的两个侧壁上的栅极隔离物和设置在栅极间隔物下方的半导体衬底中的固定电荷层。产生固定电荷的元件被注入到固定电荷层中。由固定电荷层感应的载流子被累积的层设置在固定电荷层的下方。元件通过加热从半导体衬底的内部分离到半导体衬底的衬底。

4. 发明申请

US20060249760A1 HIGH-VOLTAGE TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：半导体器件的高电压晶体管及其形成方法
公开(公告)号：US20060249760A1
公开(公告)日：2006-11-09
申请号：US11379206
申请日：2006-04-18
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Tai-Su Park , Jin-Wook LEE , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Tai-Su Park , Jin-Wook LEE , Guk-Hyon Yon
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/1045 , H01L29/66659 , H01L29/78
摘要： There are provided a high-voltage transistor and a method of forming the same. A channel region of the high-voltage transistor includes a first region and a second region. The first region has high impurity concentration that is higher than that of the second region. In addition, the first region may be in contact with the isolation layer. Thus, it is possible to enhance leakage current characteristics of the high-voltage transistor.
摘要翻译：提供了高压晶体管及其形成方法。高压晶体管的沟道区域包括第一区域和第二区域。第一区域的杂质浓度高于第二区域。此外，第一区域可以与隔离层接触。因此，可以提高高压晶体管的漏电流特性。

5. 发明申请

US20070215959A1 Semiconductor structures including accumulations of silicon boronide and related methods 审中-公开
标题翻译：半导体结构包括硅化硼的积累和相关方法
公开(公告)号：US20070215959A1
公开(公告)日：2007-09-20
申请号：US11713877
申请日：2007-03-05
申请人： Jin-Wook Lee , Chang-Woo Ryoo , Tai-Su Park , U-In Chung , Yu-Gyun Shin
发明人： Jin-Wook Lee , Chang-Woo Ryoo , Tai-Su Park , U-In Chung , Yu-Gyun Shin
IPC分类号： H01L29/94
CPC分类号： H01L29/4941 , H01L21/28061
摘要： A semiconductor device may include a semiconductor substrate, first and second source/drain regions on a surface of the semiconductor substrate, and a channel region on the surface of the semiconductor substrate with the channel region between the first and second source/drain regions. An insulating layer pattern may be on the channel region, a first conductive layer pattern may be on the insulating layer, and a second conductive layer pattern may be on the first conductive layer pattern. The insulating layer pattern may be between the first conductive layer pattern and the channel region, and the first conductive layer pattern may include boron doped polysilicon with a surface portion having an accumulation of silicon boronide. The first conductive layer pattern may be between the second conductive layer pattern and the insulating layer pattern, and the second conductive layer pattern may include tungsten. Related methods are also discussed.
摘要翻译：半导体器件可以包括半导体衬底，半导体衬底的表面上的第一和第二源极/漏极区域以及在第一和第二源极/漏极区域之间具有沟道区域的半导体衬底的表面上的沟道区域。绝缘层图案可以在沟道区上，第一导电层图案可以在绝缘层上，并且第二导电层图案可以在第一导电层图案上。绝缘层图案可以在第一导电层图案和沟道区之间，并且第一导电层图案可以包括硼掺杂多晶硅，表面部分具有硅化硼的积累。第一导电层图案可以在第二导电层图案和绝缘层图案之间，并且第二导电层图案可以包括钨。还讨论了相关方法。

6. 发明授权

US07514744B2 Semiconductor device including carrier accumulation layers 失效
标题翻译：半导体器件包括载流子堆积层
公开(公告)号：US07514744B2
公开(公告)日：2009-04-07
申请号：US11322335
申请日：2005-12-30
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Soo-Jin Hong , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Soo-Jin Hong , Guk-Hyon Yon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/4983 , H01L21/28247 , H01L21/28273 , H01L21/28282 , H01L29/6659 , H01L29/7833 , H01L29/7881 , H01L29/792
摘要： A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.
摘要翻译：半导体器件包括与半导体衬底的与源极/漏极区域相邻的沟道区域上的栅极结构，以及直接位于与栅极结构相邻的衬底的源极/漏极区域上的表面绝缘层。该器件还包括邻近源极/漏极区的栅极结构的侧壁上的间隔物。与栅极结构相邻的表面绝缘层的一部分夹在基板和间隔件之间。表面绝缘层与源极/漏极区之间的界面包括多个界面状态。紧邻界面的源极/漏极区域的部分限定了具有比其它部分更大的载流子浓度的载流子积累层。载体积聚层沿着间隔物下的界面延伸。还讨论了相关方法。

7. 发明授权

US07492006B2 Semiconductor transistors having surface insulation layers and methods of fabricating such transistors 失效
标题翻译：具有表面绝缘层的半导体晶体管和制造这种晶体管的方法
公开(公告)号：US07492006B2
公开(公告)日：2009-02-17
申请号：US11215217
申请日：2005-08-30
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Sang-Jin Hyun , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Sang-Jin Hyun , Guk-Hyon Yon
IPC分类号： H01L23/62
CPC分类号： H01L29/4983 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/7881 , H01L29/792
摘要： Semiconductor devices having a transistor and methods of fabricating such devices are disclosed. The device may include a gate pattern formed on a substrate, spacers formed on sidewalls of the gate pattern, a surface insulation layer that may contact the substrate is interposed between the spacers and the substrate. An inversion layer is provided in the surface region of the substrate under the surface insulation layer. The surface insulation layer is formed of a material generating large quantities of surface states at an interface between the substrate and the surface insulation layer.
摘要翻译：公开了具有晶体管的半导体器件及其制造方法。器件可以包括形成在衬底上的栅极图案，形成在栅极图案的侧壁上的间隔物，可以接触衬底的表面绝缘层插入在衬垫和衬底之间。在表面绝缘层下方的基板的表面区域设置反转层。表面绝缘层由在基板和表面绝缘层之间的界面处产生大量表面状态的材料形成。

8. 发明申请

US20060060929A1 Semiconductor transistors having surface insulation layers and methods of fabricating such transistors 失效
公开(公告)号：US20060060929A1
公开(公告)日：2006-03-23
申请号：US11215217
申请日：2005-08-30
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Sang-Yin Hyun , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Sang-Yin Hyun , Guk-Hyon Yon
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/4983 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/7881 , H01L29/792
摘要： Semiconductor devices having a transistor and methods of fabricating such devices are disclosed. The device may include a gate pattern formed on a substrate, spacers formed on sidewalls of the gate pattern, a surface insulation layer that may contact the substrate is interposed between the spacers and the substrate. An inversion layer is provided in the surface region of the substrate under the surface insulation layer. The surface insulation layer is formed of a material generating large quantities of surface states at an interface between the substrate and the surface insulation layer.

9. 发明申请

US20060145254A1 Semiconductor devices including carrier accumulation layers and methods for fabricating the same 失效
标题翻译：包括载体积聚层的半导体器件及其制造方法
公开(公告)号：US20060145254A1
公开(公告)日：2006-07-06
申请号：US11322335
申请日：2005-12-30
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Soo-Jin Hong , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Soo-Jin Hong , Guk-Hyon Yon
IPC分类号： H01L29/76
CPC分类号： H01L29/4983 , H01L21/28247 , H01L21/28273 , H01L21/28282 , H01L29/6659 , H01L29/7833 , H01L29/7881 , H01L29/792
摘要： A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.
摘要翻译：半导体器件包括与半导体衬底的与源极/漏极区域相邻的沟道区域上的栅极结构，以及直接位于与栅极结构相邻的衬底的源极/漏极区域上的表面绝缘层。该器件还包括邻近源极/漏极区的栅极结构的侧壁上的间隔物。与栅极结构相邻的表面绝缘层的一部分夹在基板和间隔件之间。表面绝缘层与源极/漏极区之间的界面包括多个界面状态。紧邻界面的源极/漏极区域的部分限定了具有比其它部分更大的载流子浓度的载流子积累层。载体积聚层沿着间隔物下的界面延伸。还讨论了相关方法。

10. 发明授权

US08501611B2 Methods of forming integrated circuit devices having electrically conductive layers therein with partially nitridated sidewalls 有权
标题翻译：形成其中具有部分氮化侧壁的导电层的集成电路器件的方法
公开(公告)号：US08501611B2
公开(公告)日：2013-08-06
申请号：US13551251
申请日：2012-07-17
申请人： Jeong-Do Ryu , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Dong-Chan Kim , Jong-Ryeol Yoo , Seong-Hoon Jeong , Jong-Hoon Kang
发明人： Jeong-Do Ryu , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Dong-Chan Kim , Jong-Ryeol Yoo , Seong-Hoon Jeong , Jong-Hoon Kang
IPC分类号： H01L21/3205
CPC分类号： H01L21/28061 , H01L21/28247 , H01L21/3211 , H01L21/32137 , H01L21/32139 , H01L27/10873 , H01L27/11 , H01L27/1104
摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.
摘要翻译：形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。

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