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1. 发明授权

US07351622B2 Methods of forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US07351622B2
公开(公告)日：2008-04-01
申请号：US11490613
申请日：2006-07-21
申请人： Gyoung-Ho Buh , Chang-Woo Ryoo , Yu-Gyun Shin , Tai-Su Park , Jin-Wook Lee
发明人： Gyoung-Ho Buh , Chang-Woo Ryoo , Yu-Gyun Shin , Tai-Su Park , Jin-Wook Lee
IPC分类号： H01L21/84 , H01L21/8234 , H01L21/336 , H01L21/00
CPC分类号： H01L29/7851 , H01L29/42392 , H01L29/66795 , H01L29/66803
摘要： A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type impurity elements, and the second source gas includes a dilution element regardless of the electrical characteristic of a doped region.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成由半导体形成的三维结构，并且通过使用第一源气体和第二源气体进行等离子体掺杂工艺，对三维结构进行各向同性地掺杂。第一源气体包括n型或p型杂质元素，第二源气体包括稀释元件，而与掺杂区域的电特性无关。

2. 发明申请

US20070020827A1 Methods of forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US20070020827A1
公开(公告)日：2007-01-25
申请号：US11490613
申请日：2006-07-21
申请人： Gyoung-Ho Buh , Chang-Woo Ryoo , Yu-Gyun Shin , Tai-Su Park , Jin-Wook Lee
发明人： Gyoung-Ho Buh , Chang-Woo Ryoo , Yu-Gyun Shin , Tai-Su Park , Jin-Wook Lee
IPC分类号： H01L21/84 , H01L21/8234 , H01L21/336 , H01L21/00
CPC分类号： H01L29/7851 , H01L29/42392 , H01L29/66795 , H01L29/66803
摘要： A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type impurity elements, and the second source gas includes a dilution element regardless of the electrical characteristic of a doped region.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成由半导体形成的三维结构，并且通过使用第一源气体和第二源气体进行等离子体掺杂工艺，对三维结构进行各向同性地掺杂。第一源气体包括n型或p型杂质元素，第二源气体包括稀释元件，而与掺杂区域的电特性无关。

3. 发明申请

US20060249760A1 HIGH-VOLTAGE TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：半导体器件的高电压晶体管及其形成方法
公开(公告)号：US20060249760A1
公开(公告)日：2006-11-09
申请号：US11379206
申请日：2006-04-18
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Tai-Su Park , Jin-Wook LEE , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Tai-Su Park , Jin-Wook LEE , Guk-Hyon Yon
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/1045 , H01L29/66659 , H01L29/78
摘要： There are provided a high-voltage transistor and a method of forming the same. A channel region of the high-voltage transistor includes a first region and a second region. The first region has high impurity concentration that is higher than that of the second region. In addition, the first region may be in contact with the isolation layer. Thus, it is possible to enhance leakage current characteristics of the high-voltage transistor.
摘要翻译：提供了高压晶体管及其形成方法。高压晶体管的沟道区域包括第一区域和第二区域。第一区域的杂质浓度高于第二区域。此外，第一区域可以与隔离层接触。因此，可以提高高压晶体管的漏电流特性。

4. 发明申请

US20070215959A1 Semiconductor structures including accumulations of silicon boronide and related methods 审中-公开
标题翻译：半导体结构包括硅化硼的积累和相关方法
公开(公告)号：US20070215959A1
公开(公告)日：2007-09-20
申请号：US11713877
申请日：2007-03-05
申请人： Jin-Wook Lee , Chang-Woo Ryoo , Tai-Su Park , U-In Chung , Yu-Gyun Shin
发明人： Jin-Wook Lee , Chang-Woo Ryoo , Tai-Su Park , U-In Chung , Yu-Gyun Shin
IPC分类号： H01L29/94
CPC分类号： H01L29/4941 , H01L21/28061
摘要： A semiconductor device may include a semiconductor substrate, first and second source/drain regions on a surface of the semiconductor substrate, and a channel region on the surface of the semiconductor substrate with the channel region between the first and second source/drain regions. An insulating layer pattern may be on the channel region, a first conductive layer pattern may be on the insulating layer, and a second conductive layer pattern may be on the first conductive layer pattern. The insulating layer pattern may be between the first conductive layer pattern and the channel region, and the first conductive layer pattern may include boron doped polysilicon with a surface portion having an accumulation of silicon boronide. The first conductive layer pattern may be between the second conductive layer pattern and the insulating layer pattern, and the second conductive layer pattern may include tungsten. Related methods are also discussed.
摘要翻译：半导体器件可以包括半导体衬底，半导体衬底的表面上的第一和第二源极/漏极区域以及在第一和第二源极/漏极区域之间具有沟道区域的半导体衬底的表面上的沟道区域。绝缘层图案可以在沟道区上，第一导电层图案可以在绝缘层上，并且第二导电层图案可以在第一导电层图案上。绝缘层图案可以在第一导电层图案和沟道区之间，并且第一导电层图案可以包括硼掺杂多晶硅，表面部分具有硅化硼的积累。第一导电层图案可以在第二导电层图案和绝缘层图案之间，并且第二导电层图案可以包括钨。还讨论了相关方法。

5. 发明申请

US20070054453A1 Methods of forming integrated circuit memory devices having a charge storing layer formed by plasma doping 审中-公开
标题翻译：形成具有通过等离子体掺杂形成的电荷存储层的集成电路存储器件的方法
公开(公告)号：US20070054453A1
公开(公告)日：2007-03-08
申请号：US11504023
申请日：2006-08-14
申请人： Gyoung-Ho Buh , Tai-Su Park , Chang-Woo Ryoo , Jong-Ryeol Yoo , Young-Chang Song
发明人： Gyoung-Ho Buh , Tai-Su Park , Chang-Woo Ryoo , Jong-Ryeol Yoo , Young-Chang Song
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L29/42344 , H01L29/66833
摘要： Methods of forming an integrated circuit memory device include forming a dielectric layer on a substrate and forming a charge storing layer on an upper surface of the dielectric layer using a plasma doping process with a remaining portion of the dielectric layer under the charge storing layer defining a tunnel dielectric layer. A blocking dielectric layer is formed on the charge storing layer and a gate electrode layer is formed on the blocking dielectric layer.
摘要翻译：形成集成电路存储器件的方法包括在衬底上形成电介质层，并使用等离子体掺杂工艺在电介质层的上表面上形成电荷存储层，其中电荷存储层下面的介电层的剩余部分限定了隧道介电层。在电荷存储层上形成阻挡电介质层，在阻挡电介质层上形成栅电极层。

6. 发明申请

US20100072545A1 Recessed Channel Array Transistors, and Semiconductor Devices Including a Recessed Channel Array Transistor 有权
标题翻译：嵌入式通道阵列晶体管和包括嵌入式通道阵列晶体管的半导体器件
公开(公告)号：US20100072545A1
公开(公告)日：2010-03-25
申请号：US12563473
申请日：2009-09-21
申请人： Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L27/06 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/28211 , H01L21/823412 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/10894 , H01L27/11 , H01L29/4236 , H01L29/51 , H01L29/66621 , H01L29/7851
摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.
摘要翻译：凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。衬底可以具有有源区和隔离区。可以在活性区域中形成凹陷。栅极氧化物层可以形成在凹部和基板上。栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。第一部分可以包括大于第二部分厚度的约70％的厚度。栅极电极可以形成在栅极氧化物层上。源极/漏极区域可以形成在衬底中。因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。

7. 发明授权

US09190495B2 Recessed channel array transistors, and semiconductor devices including a recessed channel array transistor 有权
标题翻译：嵌入式沟道阵列晶体管和包括凹陷沟道阵列晶体管的半导体器件
公开(公告)号：US09190495B2
公开(公告)日：2015-11-17
申请号：US12563473
申请日：2009-09-21
申请人： Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L27/06 , H01L29/78 , H01L29/66 , H01L21/28 , H01L27/105 , H01L27/108 , H01L27/11 , H01L29/423 , H01L29/51 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/66795 , H01L21/28211 , H01L21/823412 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/10894 , H01L27/11 , H01L29/4236 , H01L29/51 , H01L29/66621 , H01L29/7851
摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.
摘要翻译：凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。衬底可以具有有源区和隔离区。可以在活性区域中形成凹部。栅极氧化物层可以形成在凹部和基板上。栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。第一部分可以包括大于第二部分厚度的约70％的厚度。栅极电极可以形成在栅极氧化物层上。源极/漏极区域可以形成在衬底中。因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。

8. 发明授权

US08252681B2 Methods of forming integrated circuit devices having electrically conductive layers therein with partially nitridated sidewalls 有权
标题翻译：形成其中具有部分氮化侧壁的导电层的集成电路器件的方法
公开(公告)号：US08252681B2
公开(公告)日：2012-08-28
申请号：US12536865
申请日：2009-08-06
申请人： Jeong-Do Ryu , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Dong-Chan Kim , Jong-Ryeol Yoo , Seong-Hoon Jeong , Jong-Hoon Kang
发明人： Jeong-Do Ryu , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Dong-Chan Kim , Jong-Ryeol Yoo , Seong-Hoon Jeong , Jong-Hoon Kang
IPC分类号： H01L21/44
CPC分类号： H01L21/28061 , H01L21/28247 , H01L21/3211 , H01L21/32137 , H01L21/32139 , H01L27/10873 , H01L27/11 , H01L27/1104
摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.
摘要翻译：形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。

9. 发明授权

US08691649B2 Methods of forming recessed channel array transistors and methods of manufacturing semiconductor devices 有权
标题翻译：形成凹槽阵列晶体管的方法和制造半导体器件的方法
公开(公告)号：US08691649B2
公开(公告)日：2014-04-08
申请号：US13151494
申请日：2011-06-02
申请人： Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L21/28211 , H01L21/823412 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/11 , H01L29/4236 , H01L29/51 , H01L29/66621 , H01L29/7851
摘要： In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.
摘要翻译：在制造凹陷通道阵列晶体管的方法中，可以在衬底的有源区中形成凹部。可以在衬底上进行等离子体氧化处理，以在凹槽的内表面和衬底的上表面上形成预备栅氧化层。可以在预选择栅极氧化物层的表面吸收水分以形成栅极氧化物层。可以在栅极氧化物层上形成栅电极以填充凹部。源极/漏极区域可以形成在栅电极的两侧的衬底的上表面中。因此，氧化物层可以具有均匀的厚度分布和致密结构。

10. 发明授权

US06258726B1 Method of forming isolation film for semiconductor devices 失效
标题翻译：形成半导体器件隔离膜的方法
公开(公告)号：US06258726B1
公开(公告)日：2001-07-10
申请号：US09412888
申请日：1999-10-05
申请人： Tai-Su Park , Yu-gyun Shin , Han-sin Lee , Kyung-won Park
发明人： Tai-Su Park , Yu-gyun Shin , Han-sin Lee , Kyung-won Park
IPC分类号： H01L21302
CPC分类号： H01L21/76224
摘要： A method of forming an isolation film forms a spacer for connecting the edge of an active region to the isolation film. The spacer is on the upper sidewall of a trench and smoothes the transition or step between the level of the isolation film and the level of the active region. Accordingly, a gate oxide film of a uniform thickness can be formed on the entire active region in a subsequent process, thus preventing degradation of the characteristics of the gate oxide film. The spacer can be formed using a sidewall spacer on the hard mask used for forming the trench. The sidewall spacer protects part of the isolation formed in the trench, and etching after removal of the sidewall spacer can round the protected portion to create the spacer. Furthermore, to dispel stresses and defects in the isolation film, annealing for densification of the isolation film can be performed at a high temperature such as about 1150° C. because the spacer mitigates the effects of shrinking or sagging of the isolation film.
摘要翻译：形成隔离膜的方法形成用于将有源区域的边缘连接到隔离膜的间隔物。间隔物位于沟槽的上侧壁上，并平滑了隔离膜的电平与有源区的电平之间的转变或台阶。因此，可以在随后的工艺中在整个有源区上形成均匀厚度的栅极氧化膜，从而防止栅极氧化膜的特性劣化。间隔物可以使用用于形成沟槽的硬掩模上的侧壁间隔物形成。侧壁间隔件保护形成在沟槽中的隔离部分，并且在去除侧壁间隔物之后的蚀刻可围绕被保护部分以形成隔离物。此外，为了消除隔离膜中的应力和缺陷，隔离膜的致密化退火可以在诸如约1150℃的高温下进行，因为间隔物减轻了隔离膜的收缩或下垂的影响。

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