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1. 发明申请

US20140203956A1 ANALOG-TO-DIGITAL CONVERSION IN PIXEL ARRAYS 有权
标题翻译：像素阵列中的模拟数字转换
公开(公告)号：US20140203956A1
公开(公告)日：2014-07-24
申请号：US14158818
申请日：2014-01-18
申请人： Guy Meynants , Bram WOLFS , Jan BOGAERTS
发明人： Guy Meynants , Bram WOLFS , Jan BOGAERTS
IPC分类号： H03M1/34
CPC分类号： H03M1/34 , H03M1/123 , H03M1/56 , H04N5/378
摘要： An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N≧2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.
摘要翻译：用于产生与第一模拟信号电平（Vres）和第二模拟信号电平（Vsig）之间的差相当的输出数字值的模拟 - 数字转换器包括用于接收第一模拟信号电平的至少一个输入端和第二模拟信号电平模拟信号电平，用于接收斜坡信号的输入端和用于接收至少一个时钟信号的输入端。一组N个计数器，其中N≥2，被布置成使用相互偏移的N个时钟信号。控制级被布置成基于斜坡信号与第一模拟信号电平（Vres）和第二模拟信号电平（Vsig）的比较来使N个计数器能够使能。输出级被布置为输出数字值，该数字值是在它们被使能的时段期间由N个计数器累积的值的函数。

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