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1. 发明申请

US20100262783A1 Mode-Based Castout Destination Selection 失效
标题翻译：基于模式的Castout目的地选择
公开(公告)号：US20100262783A1
公开(公告)日：2010-10-14
申请号：US12420933
申请日：2009-04-09
申请人： Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
发明人： Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/12
摘要： In response to a data request of a first of a plurality of processing units, the first processing unit selects a victim cache line to be castout from the lower level cache of the first processing unit and determines whether a mode is set. If not, the first processing unit issues on the interconnect fabric an LCO command identifying the victim cache line and indicating that a lower level cache is the intended destination. If the mode is set, the first processing unit issues a castout command with an alternative intended destination. In response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache, and the victim cache line is held elsewhere in the data processing system. The mode can be set to inhibit castouts to system memory, for example, for testing.
摘要翻译：响应于多个处理单元中的第一处理单元的数据请求，第一处理单元从第一处理单元的较低级高速缓存中选择要丢弃的牺牲高速缓存行，并且确定是否设置了模式。如果不是，则第一处理单元在互连结构上发出识别受害者高速缓存行的LCO命令，并指示较低级别的高速缓存是预期的目的地。如果模式被设置，则第一处理单元发出具有替代预定目的地的停顿命令。响应于指示LCO命令成功的LCO命令的一致性响应，第一处理单元从其较低级高速缓存中去除受害者高速缓存行，并且将受害者高速缓存行保持在数据处理系统的其他地方。该模式可以设置为抑制系统内存的丢弃，例如进行测试。

2. 发明授权

US08312220B2 Mode-based castout destination selection 失效
标题翻译：基于模式的castout目的地选择
公开(公告)号：US08312220B2
公开(公告)日：2012-11-13
申请号：US12420933
申请日：2009-04-09
申请人： Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Phillip G. Williams , Jeffrey A. Stuecheli
发明人： Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Phillip G. Williams , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/12
摘要： In response to a data request of a first of a plurality of processing units, the first processing unit selects a victim cache line to be castout from the lower level cache of the first processing unit and determines whether a mode is set. If not, the first processing unit issues on the interconnect fabric an LCO command identifying the victim cache line and indicating that a lower level cache is the intended destination. If the mode is set, the first processing unit issues a castout command with an alternative intended destination. In response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache, and the victim cache line is held elsewhere in the data processing system. The mode can be set to inhibit castouts to system memory, for example, for testing.
摘要翻译：响应于多个处理单元中的第一处理单元的数据请求，第一处理单元从第一处理单元的较低级高速缓存中选择要丢弃的牺牲高速缓存行，并且确定是否设置了模式。如果不是，则第一处理单元在互连结构上发出识别受害者高速缓存行的LCO命令，并指示较低级别的高速缓存是预期的目的地。如果模式被设置，则第一处理单元发出具有替代预定目的地的停顿命令。响应于指示LCO命令成功的LCO命令的一致性响应，第一处理单元从其较低级高速缓存中去除受害者高速缓存行，并且将受害者高速缓存行保持在数据处理系统的其他地方。该模式可以设置为抑制系统内存的丢弃，例如进行测试。

3. 发明申请

US20100262778A1 Empirically Based Dynamic Control of Transmission of Victim Cache Lateral Castouts 有权
标题翻译：基于经验的动态控制受害者缓存横向铸件传动
公开(公告)号：US20100262778A1
公开(公告)日：2010-10-14
申请号：US12421180
申请日：2009-04-09
申请人： Robert A. Cargnoni , Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
发明人： Robert A. Cargnoni , Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0862 , G06F12/127 , G06F2212/6026
摘要： In response to a data request, a victim cache line is selected for castout from a lower level cache, and a target lower level cache of one of the plurality of processing units is selected. A determination is made whether the selected target lower level cache has provided more than a threshold number of retry responses to lateral castout (LCO) commands of the first lower level cache, and if so, a different target lower level cache is selected. The first processing unit thereafter issues a LCO command on the interconnect fabric. The LCO command identifies the victim cache line to be castout and indicates that the target lower level cache is an intended destination of the victim cache line. In response to a successful coherence response to the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.
摘要翻译：响应于数据请求，选择从较低级别高速缓冲存储器进行丢弃的受害者高速缓存行，并且选择多个处理单元之一的目标下级高速缓存。确定所选择的目标下层高速缓存是否为第一较低级别高速缓存的横向转移（LCO）命令提供了超过阈值数量的重试响应，如果是，则选择不同的目标低级高速缓存。此后，第一处理单元在互连结构上发出LCO命令。 LCO命令标识要丢弃的受害者缓存行，并指示目标下级缓存是受害缓存行的预期目标。响应于对LCO命令的成功的一致性响应，从第一低级缓存中移除受害者高速缓存行并保存在第二较低级缓存中。

4. 发明授权

US08347036B2 Empirically based dynamic control of transmission of victim cache lateral castouts 有权
标题翻译：基于经验的动态控制受害者缓存横向传播的传输
公开(公告)号：US08347036B2
公开(公告)日：2013-01-01
申请号：US12421180
申请日：2009-04-09
申请人： Robert A. Cargnoni , Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
发明人： Robert A. Cargnoni , Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0862 , G06F12/127 , G06F2212/6026
摘要： In response to a data request, a victim cache line is selected for castout from a lower level cache, and a target lower level cache of one of the plurality of processing units is selected. A determination is made whether the selected target lower level cache has provided more than a threshold number of retry responses to lateral castout (LCO) commands of the first lower level cache, and if so, a different target lower level cache is selected. The first processing unit thereafter issues a LCO command on the interconnect fabric. The LCO command identifies the victim cache line to be castout and indicates that the target lower level cache is an intended destination of the victim cache line. In response to a successful coherence response to the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.
摘要翻译：响应于数据请求，选择从较低级别高速缓冲存储器进行丢弃的受害者高速缓存行，并且选择多个处理单元之一的目标下级高速缓存。确定所选择的目标下层高速缓存是否为第一较低级别高速缓存的横向转移（LCO）命令提供了超过阈值数量的重试响应，如果是，则选择不同的目标低级高速缓存。此后，第一处理单元在互连结构上发出LCO命令。 LCO命令标识要丢弃的受害者缓存行，并指示目标下级缓存是受害缓存行的预期目标。响应于对LCO命令的成功的一致性响应，从第一低级缓存中移除受害者高速缓存行并保存在第二较低级缓存中。

5. 发明申请

US20100262784A1 Empirically Based Dynamic Control of Acceptance of Victim Cache Lateral Castouts 有权
标题翻译：基于经验的动态控制接受受害者缓存横向铸件
公开(公告)号：US20100262784A1
公开(公告)日：2010-10-14
申请号：US12421017
申请日：2009-04-09
申请人： Guy L. Guthrie , Harmony L. Helterhoff , Thomas L. Jeremiah , Alvan W. Ng , William J. Starke , Jeffrey A. Stuecheli , Philip G. Williams
发明人： Guy L. Guthrie , Harmony L. Helterhoff , Thomas L. Jeremiah , Alvan W. Ng , William J. Starke , Jeffrey A. Stuecheli , Philip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/0811 , G06F12/0815 , G06F12/0862
摘要： A second lower level cache receives an LCO command issued by a first lower level cache on an interconnect fabric. The LCO command indicates an address of a victim cache line to be castout from the first lower level cache and indicates that the second lower level cache is an intended destination of the victim cache line. The second lower level cache determines whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command. In response to determining not to accept the victim cache line, the second lower level cache provides a coherence response to the LCO command refusing the identified victim cache line. In response to determining to accept the victim cache line, the second lower level cache updates an entry corresponding to the identified victim cache line.
摘要翻译：第二低级缓存接收由互连结构上的第一较低级缓存发出的LCO命令。 LCO命令指示要从第一较低级高速缓存丢弃的受害者高速缓存行的地址，并且指示第二较低级高速缓存是受害者高速缓存行的预期目的地。第二较低级缓存至少部分地基于由LCO命令指示的受害缓存行的地址来确定是否从第一低级缓存接受受害者高速缓存行。响应于确定不接受受害者缓存行，第二较低级缓存为LCO命令提供拒绝所识别的受害者缓存行的一致性响应。响应于确定接受受害者缓存行，第二较低级缓存更新对应于所识别的受害者高速缓存行的条目。

6. 发明授权

US08327073B2 Empirically based dynamic control of acceptance of victim cache lateral castouts 有权
标题翻译：基于经验的动态控制接受受害者缓存横向突出
公开(公告)号：US08327073B2
公开(公告)日：2012-12-04
申请号：US12421017
申请日：2009-04-09
申请人： Guy L. Guthrie , Harmony L. Helterhoff , Thomas L. Jeremiah , Alvan W. Ng , William J. Starke , Jeffrey A. Stuecheli , Philip G. Williams
发明人： Guy L. Guthrie , Harmony L. Helterhoff , Thomas L. Jeremiah , Alvan W. Ng , William J. Starke , Jeffrey A. Stuecheli , Philip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/0811 , G06F12/0815 , G06F12/0862
摘要： A second lower level cache receives an LCO command issued by a first lower level cache on an interconnect fabric. The LCO command indicates an address of a victim cache line to be castout from the first lower level cache and indicates that the second lower level cache is an intended destination of the victim cache line. The second lower level cache determines whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command. In response to determining not to accept the victim cache line, the second lower level cache provides a coherence response to the LCO command refusing the identified victim cache line. In response to determining to accept the victim cache line, the second lower level cache updates an entry corresponding to the identified victim cache line.
摘要翻译：第二低级缓存接收由互连结构上的第一较低级缓存发出的LCO命令。 LCO命令指示要从第一较低级高速缓存丢弃的受害者高速缓存行的地址，并且指示第二较低级高速缓存是受害者高速缓存行的预期目的地。第二较低级缓存至少部分地基于由LCO命令指示的受害缓存行的地址来确定是否从第一低级缓存接受受害者高速缓存行。响应于确定不接受受害者缓存行，第二较低级缓存为LCO命令提供拒绝所识别的受害者缓存行的一致性响应。响应于确定接受受害者缓存行，第二较低级缓存更新对应于所识别的受害者高速缓存行的条目。

7. 发明授权

US08209489B2 Victim cache prefetching 失效
标题翻译：受害者缓存预取
公开(公告)号：US08209489B2
公开(公告)日：2012-06-26
申请号：US12256064
申请日：2008-10-22
申请人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
发明人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0897 , Y02D10/13
摘要： A processing unit for a multiprocessor data processing system includes a processor core and a cache hierarchy coupled to the processor core to provide low latency data access. The cache hierarchy includes an upper level cache coupled to the processor core and a lower level victim cache coupled to the upper level cache. In response to a prefetch request of the processor core that misses in the upper level cache, the lower level victim cache determines whether the prefetch request misses in the directory of the lower level victim cache and, if so, allocates a state machine in the lower level victim cache that services the prefetch request by issuing the prefetch request to at least one other processing unit of the multiprocessor data processing system.
摘要翻译：用于多处理器数据处理系统的处理单元包括处理器核心和耦合到处理器核心的高速缓存层级以提供低延迟数据访问。高速缓存层级包括耦合到处理器核心的高级缓存和耦合到高级缓存的较低级别的牺牲缓存。响应于在高级缓存中丢失的处理器核心的预取请求，较低级别的受害者缓存确定预取请求是否丢失在较低级别的受害者缓存的目录中，并且如果是，则在下级缓存中分配状态机通过向多处理器数据处理系统的至少一个其他处理单元发出预取请求来服务于预取请求。

8. 发明授权

US07454578B2 Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory 有权
标题翻译：数据处理系统和方法，用于使用存储器的位置预测性地选择操作的广播范围
公开(公告)号：US07454578B2
公开(公告)日：2008-11-18
申请号：US11055697
申请日：2005-02-10
申请人： James S. Fields, Jr. , Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
发明人： James S. Fields, Jr. , Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
IPC分类号： G06F13/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes a memory and at least first and second coherency domains that each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation targeting a request address allocated to the memory from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains. The master selects the scope based, at least in part, upon whether the memory belongs to the first coherency domain and performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.
摘要翻译：高速缓存一致数据处理系统包括存储器和至少第一和第二一致性域，每个域包括第一和第二高速缓存存储器中的相应一个。第一相干域中的主机从仅包括第一相关域的第一范围和包括第一和第二相干域的第二范围中选择针对分配给存储器的请求地址的操作的初始广播的范围。主设备至少部分地基于所述存储器是否属于第一相关域并且使用所选择的范围来执行在高速缓存相干数据处理系统内的操作的初始广播来选择所述范围。

9. 发明授权

US09176876B2 Selective cache-to-cache lateral castouts 有权
公开(公告)号：US09176876B2
公开(公告)日：2015-11-03
申请号：US13445646
申请日：2012-04-12
申请人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams , Thomas R. Puzak
发明人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams , Thomas R. Puzak
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/12
摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.

10. 发明授权

US08103791B2 Synchronized communication in a data processing system 失效
标题翻译：数据处理系统中的同步通信
公开(公告)号：US08103791B2
公开(公告)日：2012-01-24
申请号：US12195130
申请日：2008-08-20
申请人： Benjiman L. Goodman , Guy L. Guthrie , Praveen S. Reddy , William J. Starke , Jeffrey A. Stuecheli
发明人： Benjiman L. Goodman , Guy L. Guthrie , Praveen S. Reddy , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F15/173 , G06F12/00 , G06F13/14 , G06F1/04 , G06F1/12
CPC分类号： G06F15/16
摘要： A data processing system includes a plurality of processing units, including at least a local master and a local hub, which are coupled for communication via a communication link. The local master includes a master capable of initiating an operation, a snooper capable of receiving an operation, and interconnect logic coupled to a communication link coupling the local master to the local hub. The interconnect logic includes request logic that synchronizes internal transmission of a request of the master to the snooper with transmission, via the communication link, of the request to the local hub.
摘要翻译：数据处理系统包括多个处理单元，至少包括本地主站和本地集线器，其经由通信链路进行通信。本地主机包括能够启动操作的主机，能够接收操作的监听器，以及耦合到将本地主机耦合到本地集线器的通信链路的逻辑互连。互连逻辑包括请求逻辑，其将主机的请求的内部传输与通过通信链路传送到本地集线器的请求同步到窥探者的请求逻辑。

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