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1. 发明申请

US20140086070A1 Bandwidth Management 有权
标题翻译：带宽管理
公开(公告)号：US20140086070A1
公开(公告)日：2014-03-27
申请号：US13625416
申请日：2012-09-24
申请人： Gurjeet S. Saund , James B. Keller , Manu Gulati , Sukalpa Biswas
发明人： Gurjeet S. Saund , James B. Keller , Manu Gulati , Sukalpa Biswas
IPC分类号： H04L12/26
CPC分类号： G06F13/1605 , Y02D10/14
摘要： In some embodiments, a system includes a shared, high bandwidth resource (e.g. a memory system), multiple agents configured to communicate with the shared resource, and a communication fabric coupling the multiple agents to the shared resource. The communication fabric may be equipped with limiters configured to limit bandwidth from the various agents based on one or more performance metrics measured with respect to the shared, high bandwidth resource. For example, the performance metrics may include one or more of latency, number of outstanding transactions, resource utilization, etc. The limiters may dynamically modify their limit configurations based on the performance metrics. In an embodiment, the system may include multiple thresholds for the performance metrics, and exceeding a given threshold may include modifying the limiters in the communication fabric. There may be hysteresis implemented in the system as well in some embodiments, to reduce the frequency of transitions between configurations.
摘要翻译：在一些实施例中，系统包括共享的高带宽资源（例如，存储器系统），被配置为与共享资源通信的多个代理以及将多个代理耦合到共享资源的通信结构。通信结构可以配备有限制器，其被配置为基于针对共享的高带宽资源测量的一个或多个性能度量来限制来自各种代理的带宽。例如，性能度量可以包括延迟，未决事务数量，资源利用等中的一个或多个。限制器可以基于性能度量动态修改其限制配置。在一个实施例中，系统可以包括用于性能度量的多个阈值，并且超过给定阈值可以包括修改通信结构中的限制器。在一些实施例中，也可能在系统中实现滞后，以减少配置之间的转换频率。

2. 发明授权

US08848577B2 Bandwidth management 有权
标题翻译：带宽管理
公开(公告)号：US08848577B2
公开(公告)日：2014-09-30
申请号：US13625416
申请日：2012-09-24
申请人： Gurjeet S. Saund , James B. Keller , Manu Gulati , Sukalpa Biswas
发明人： Gurjeet S. Saund , James B. Keller , Manu Gulati , Sukalpa Biswas
IPC分类号： H04L12/28
CPC分类号： G06F13/1605 , Y02D10/14
摘要： In some embodiments, a system includes a shared, high bandwidth resource (e.g. a memory system), multiple agents configured to communicate with the shared resource, and a communication fabric coupling the multiple agents to the shared resource. The communication fabric may be equipped with limiters configured to limit bandwidth from the various agents based on one or more performance metrics measured with respect to the shared, high bandwidth resource. For example, the performance metrics may include one or more of latency, number of outstanding transactions, resource utilization, etc. The limiters may dynamically modify their limit configurations based on the performance metrics. In an embodiment, the system may include multiple thresholds for the performance metrics, and exceeding a given threshold may include modifying the limiters in the communication fabric. There may be hysteresis implemented in the system as well in some embodiments, to reduce the frequency of transitions between configurations.
摘要翻译：在一些实施例中，系统包括共享的高带宽资源（例如，存储器系统），被配置为与共享资源通信的多个代理以及将多个代理耦合到共享资源的通信结构。通信结构可以配备有限制器，其被配置为基于针对共享的高带宽资源测量的一个或多个性能度量来限制来自各种代理的带宽。例如，性能度量可以包括延迟，未决事务数量，资源利用等中的一个或多个。限制器可以基于性能度量动态修改其限制配置。在一个实施例中，系统可以包括用于性能度量的多个阈值，并且超过给定阈值可以包括修改通信结构中的限制器。在一些实施例中，也可能在系统中实现滞后，以减少配置之间的转换频率。

3. 发明授权

US08649286B2 Quality of service (QoS)-related fabric control 有权
标题翻译：服务质量（QoS）相关的结构控制
公开(公告)号：US08649286B2
公开(公告)日：2014-02-11
申请号：US13008180
申请日：2011-01-18
申请人： Gurjeet S. Saund , Sukalpa Biswas , Brijesh Tripathi
发明人： Gurjeet S. Saund , Sukalpa Biswas , Brijesh Tripathi
IPC分类号： G06F13/38
CPC分类号： H04L49/356 , H04L49/354
摘要： In an embodiment, one or more fabric control circuits may be inserted in a communication fabric to control various aspects of the communications by components in the system. The fabric control circuits may be included on the interface of the components to the communication fabric, in some embodiments. In other embodiments that include a hierarchical communication fabric, fabric control circuits may alternatively or additionally be included. The fabric control circuits may be programmable, and thus may provide the ability to tune the communication fabric to meet performance and/or functionality goals.
摘要翻译：在一个实施例中，可以将一个或多个结构控制电路插入到通信结构中，以通过系统中的组件来控制通信的各个方面。在一些实施例中，结构控制电路可以包括在组件的接口上到通信结构。在包括分层通信结构的其他实施例中，结构控制电路可以可选地或另外包括。织物控制电路可以是可编程的，因此可以提供调谐通信结构以满足性能和/或功能目标的能力。

4. 发明申请

US20120182889A1 Quality of Service (QoS)-Related Fabric Control 有权
标题翻译：服务质量（QoS）相关的织物控制
公开(公告)号：US20120182889A1
公开(公告)日：2012-07-19
申请号：US13008180
申请日：2011-01-18
申请人： Gurjeet S. Saund , Sukalpa Biswas , Brijesh Tripathi
发明人： Gurjeet S. Saund , Sukalpa Biswas , Brijesh Tripathi
IPC分类号： H04L12/56 , H04L12/26
CPC分类号： H04L49/356 , H04L49/354
摘要： In an embodiment, one or more fabric control circuits may be inserted in a communication fabric to control various aspects of the communications by components in the system. The fabric control circuits may be included on the interface of the components to the communication fabric, in some embodiments. In other embodiments that include a hierarchical communication fabric, fabric control circuits may alternatively or additionally be included. The fabric control circuits may be programmable, and thus may provide the ability to tune the communication fabric to meet performance and/or functionality goals.
摘要翻译：在一个实施例中，可以将一个或多个结构控制电路插入到通信结构中，以通过系统中的组件来控制通信的各个方面。在一些实施例中，结构控制电路可以包括在组件的接口上到通信结构。在包括分层通信结构的其他实施例中，结构控制电路可以可选地或另外包括。织物控制电路可以是可编程的，因此可以提供调谐通信结构以满足性能和/或功能目标的能力。

5. 发明授权

US08301941B2 Memory controller with loopback test interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US08301941B2
公开(公告)日：2012-10-30
申请号：US13305202
申请日：2011-11-28
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G01R31/28 , G11C29/00 , G06F11/00
CPC分类号： G01R31/31716
摘要： An apparatus may include an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller may be programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller may be configured to receive a first write operation from the processor over the interconnect. The memory controller may be configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller may be further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：设备可以包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可以由处理器编程成环回测试操作模式，并且在回送测试模式中，存储器控制器可以被配置为通过互连从处理器接收第一写入操作。存储器控制器可以被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。存储器控制器还可以被配置为在互连上将读数据作为读数据返回，用于从互连上的处理器接收到的第一读操作。

6. 发明申请

US20120072787A1 Memory Controller with Loopback Test Interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US20120072787A1
公开(公告)日：2012-03-22
申请号：US13305202
申请日：2011-11-28
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G01R31/28 , G06F11/26
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

7. 发明授权

US07836372B2 Memory controller with loopback test interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US07836372B2
公开(公告)日：2010-11-16
申请号：US11760566
申请日：2007-06-08
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

8. 发明申请

US20080307276A1 Memory Controller with Loopback Test Interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US20080307276A1
公开(公告)日：2008-12-11
申请号：US11760566
申请日：2007-06-08
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G11C29/04 , G06F12/00
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

9. 发明授权

US08086915B2 Memory controller with loopback test interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US08086915B2
公开(公告)日：2011-12-27
申请号：US12909073
申请日：2010-10-21
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G01R31/28 , G11C29/00 , G06F11/00
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

10. 发明申请

US20110035560A1 Memory Controller with Loopback Test Interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US20110035560A1
公开(公告)日：2011-02-10
申请号：US12909073
申请日：2010-10-21
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

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