专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06051485A Method of producing a platinum-metal pattern or structure by a lift-off process 失效
标题翻译：通过剥离工艺制造铂金属图案或结构的方法
公开(公告)号：US06051485A
公开(公告)日：2000-04-18
申请号：US66245
申请日：1998-04-24
申请人： Gunther Schindler , Walter Hartner , Dana Pitzer
发明人： Gunther Schindler , Walter Hartner , Dana Pitzer
IPC分类号： H01L21/285 , H01L21/02 , H01L21/28 , H01L21/3205 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： H01L28/60
摘要： A method of producing a platinum-metal structure or pattern on a substrate, which includes the steps of applying a silicon oxide layer to the substrate; applying a mask to the silicon oxide layer which is formed with an opening at a location thereof at which the platinum-metal structure or pattern is to be produced; etching the silicon oxide layer so that the substrate surface area exposed by the opening formed in the mask is larger than the opening in the mask; applying a platinum-metal layer to the mask and the exposed substrate surface area; and removing the silicon oxide layer in an etching process, so that the platinum metal present on the mask is removed simultaneously therewith, and the platinum metal present on the substrate surface forms the platinum-metal pattern or structure.
摘要翻译：一种在基板上制造铂金属结构或图案的方法，包括以下步骤：向基板施加氧化硅层; 在形成有铂金属结构或图案的位置处形成有开口的氧化硅层上施加掩模; 蚀刻氧化硅层，使得由形成在掩模中的开口露出的衬底表面积大于掩模中的开口; 将铂金层施加到掩模和暴露的基底表面区域; 并且在蚀刻工艺中除去氧化硅层，使得存在于掩模上的铂金属与其同时被除去，存在于衬底表面上的铂金属形成铂金属图案或结构。

2. 发明授权

US6136659A Production process for a capacitor electrode formed of a platinum metal 失效
标题翻译：由铂金属形成的电容器电极的制造方法
公开(公告)号：US6136659A
公开(公告)日：2000-10-24
申请号：US47850
申请日：1998-03-25
申请人： Gunther Schindler , Walter Hartner , Volker Weinrich , Carlos Mazure-Espejo
发明人： Gunther Schindler , Walter Hartner , Volker Weinrich , Carlos Mazure-Espejo
IPC分类号： H01L27/108 , H01L21/02 , H01L21/3213 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L21/20
CPC分类号： H01L28/65 , H01L21/32137
摘要： A production process for a capacitor electrode formed of a platinum metal includes producing a conductive electrode body on a substrate having a silicon-containing surface for the capacitor electrode. Platinum is deposited over the full surface, the platinum is silicized in a temperature step outside the electrode body and the platinum silicide is removed. The advantage of the invention is the avoidance of an etching process for metallic platinum.
摘要翻译：由铂金属形成的电容器电极的制造方法包括在具有用于电容器电极的含硅表面的基板上制造导电电极体。铂在整个表面上沉积，铂在电极体外部的温度阶段被硅化，除去铂硅化物。本发明的优点是避免金属铂的蚀刻工艺。

3. 发明授权

US6097050A Memory configuration with self-aligning non-integrated capacitor configuration 失效
标题翻译：具有自对准非集成电容配置的存储器配置
公开(公告)号：US6097050A
公开(公告)日：2000-08-01
申请号：US282041
申请日：1999-03-30
申请人： Walter Hartner , Gunther Schindler , Carlos Mazure-Espejo
发明人： Walter Hartner , Gunther Schindler , Carlos Mazure-Espejo
IPC分类号： H01L25/18 , H01L21/60 , H01L25/00 , H01L25/04 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/72
CPC分类号： H01L27/11502 , H01L24/81 , H01L2224/10135 , H01L2224/10165 , H01L2224/16237 , H01L2224/81139 , H01L2224/8114 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01041 , H01L2924/01056 , H01L2924/01073 , H01L2924/01082 , H01L2924/19041 , H01L2924/19043
摘要： A memory configuration with a self-aligning non-integrated capacitor configuration includes a capacitor configuration and a transistor configuration which can be joined together in a self-aligning manner in such a way that each first contact of a transistor of the transistor configuration is connected to a respective second contact of a memory capacitor of the capacitor configuration. In order to align the two configurations, the second contacts are constructed in a protruding manner, and when joining takes place they engage in a structure including elevations.
摘要翻译：具有自对准非集成电容器配置的存储器配置包括电容器配置和晶体管配置，其可以以自对准方式连接在一起，使得晶体管配置的晶体管的每个第一接触连接到电容器配置的存储电容器的相应的第二接触。为了对准这两种结构，第二触头以突出的方式构造，并且当接合发生时，它们接合包括高度的结构。

4. 发明授权

US6043529A Semiconductor configuration with a protected barrier for a stacked cell 失效
标题翻译：具有用于堆叠单元的受保护屏障的半导体构造
公开(公告)号：US6043529A
公开(公告)日：2000-03-28
申请号：US282099
申请日：1999-03-30
申请人： Walter Hartner , Gunther Schindler , Carlos Mazure-Espejo
发明人： Walter Hartner , Gunther Schindler , Carlos Mazure-Espejo
IPC分类号： H01L21/02 , H01L21/8246 , H01L29/78
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： The invention relates to a semiconductor configuration for integrated circuits, in which a stacked cell has a contact hole filled with a plug in an insulating layer, a capacitor having a lower electrode, which faces the plug, a paraelectric or ferroelectric dielectric and an upper electrode being provided on the contact hole. A barrier layer is situated between the plug and the lower electrode and is surrounded by a silicon nitride collar, which reliably prevents oxidation of the barrier layer.
摘要翻译：本发明涉及一种用于集成电路的半导体结构，其中堆叠单元具有填充有绝缘层的插塞的接触孔，具有面向插塞的下电极的电容器，顺电或铁电电介质和上电极设置在接触孔上。阻挡层位于插塞和下电极之间，并且被氮化硅套环围绕，可靠地防止阻挡层的氧化。

5. 发明授权

US5962069A Process for fabricating layered superlattice materials and AB0.sub.3 type metal oxides without exposure to oxygen at high temperatures 失效
标题翻译：用于在高温下不暴露于氧气的层压超晶格材料和AB03型金属氧化物的制造方法
公开(公告)号：US5962069A
公开(公告)日：1999-10-05
申请号：US900270
申请日：1997-07-25
申请人： Gunther Schindler , Walter Hartner , Carlos Mazure , Narayan Solayappan , Vikram Joshi , Gary F. Derbenwick
发明人： Gunther Schindler , Walter Hartner , Carlos Mazure , Narayan Solayappan , Vikram Joshi , Gary F. Derbenwick
IPC分类号： C23C18/12 , H01L21/314 , H01L21/316 , B05D3/02 , H01L21/3205
CPC分类号： H01L21/31691 , C23C18/1216 , C23C18/1225 , C23C18/1275 , C23C18/1283 , C23C18/1295
摘要： A liquid precursor containing a metal is applied to a first electrode, dried in air at a first temperature of 160.degree. C. and then a second temperature of 260.degree. C., RTP baked at a temperature of 300.degree. C. in oxygen, RTP baked at a temperature of 650.degree. C. in nitrogen, and annealed at a temperature of 800.degree. C. in nitrogen to form a strontium bismuth tantalate layered superlattice material. A second electrode is deposited and then the device is patterned to form a capacitor, and a second anneal is performed at a temperature of 800.degree. C. in nitrogen. Alternatively, the second anneal may be performed in oxygen at a temperature of 600.degree. C. or less. In this manner, a high electronic quality thin film of a layered superlattice material is fabricated without a high-temperature oxygen anneal.
摘要翻译：将含有金属的液体前体施加到第一电极上，在空气中在160℃的第一温度下干燥，然后在260℃的第二温度下干燥，在氧气中在300℃下进行RTP烘焙，RTP 在氮气中在650℃下烘烤，并在氮气中在800℃的温度下退火，形成钽酸铋锶层状超晶格材料。沉积第二电极，然后将器件图案化以形成电容器，并且在氮气中在800℃的温度下进行第二次退火。或者，第二退火可以在600℃以下的温度下进行。以这种方式，在没有高温氧退火的情况下制造层状超晶格材料的高电子质量薄膜。

6. 发明授权

US07422940B2 Layer arrangement 有权
标题翻译：层布置
公开(公告)号：US07422940B2
公开(公告)日：2008-09-09
申请号：US11195332
申请日：2005-08-01
申请人： Gunther Schindler , Werner Pamler
发明人： Gunther Schindler , Werner Pamler
IPC分类号： H01L21/8234
CPC分类号： H01L21/76885 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A process for producing a layer arrangement, in which a plurality of electrically conductive structures are formed on a substrate, a first electrically insulating layer is formed on the plurality of electrically conductive structures, in such a manner than trenches are formed between mutually adjacent regions of the first electrically insulating layer, electrically insulating structures are formed in the trenches between the adjacent regions of the first electrically insulating layer, material of the first electrically insulating layer is removed, so that airgaps are formed between the electrically insulating structures and the electrically conductive structures, and a second electrically insulating layer is formed on the electrically conductive structures and on the electrically insulating structures, in such a manner that the second electrically insulating layer spans adjacent electrically conductive structures and electrically insulating structures.
摘要翻译：一种制造其中多个导电结构形成在基板上的层布置的方法，在多个导电结构上形成第一电绝缘层，其方式不是在相互相邻的区域之间形成沟槽第一电绝缘层，电绝缘结构形成在第一电绝缘层的相邻区域之间的沟槽中，第一电绝缘层的材料被去除，使得在电绝缘结构和导电结构之间形成气隙并且在导电结构和电绝缘结构上形成第二电绝缘层，使得第二电绝缘层跨越相邻的导电结构和电绝缘结构。

7. 发明申请

US20060022345A1 Layer arrangement 有权
标题翻译：层布置
公开(公告)号：US20060022345A1
公开(公告)日：2006-02-02
申请号：US11195332
申请日：2005-08-01
申请人： Gunther Schindler , Werner Pamler
发明人： Gunther Schindler , Werner Pamler
IPC分类号： H01L21/4763 , C23C16/00 , H01L23/52
CPC分类号： H01L21/76885 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A process for producing a layer arrangement, in which a plurality of electrically conductive structures are formed on a substrate, a first electrically insulating layer is formed on the plurality of electrically conductive structures, in such a manner than trenches are formed between mutually adjacent regions of the first electrically insulating layer, electrically insulating structures are formed in the trenches between the adjacent regions of the first electrically insulating layer, material of the first electrically insulating layer is removed, so that airgaps are formed between the electrically insulating structures and the electrically conductive structures, and a second electrically insulating layer is formed on the electrically conductive structures and on the electrically insulating structures, in such a manner that the second electrically insulating layer spans adjacent electrically conductive structures and electrically insulating structures.
摘要翻译：一种制造其中多个导电结构形成在基板上的层布置的方法，在多个导电结构上形成第一电绝缘层，其方式不是在相互相邻的区域之间形成沟槽第一电绝缘层，电绝缘结构形成在第一电绝缘层的相邻区域之间的沟槽中，第一电绝缘层的材料被去除，使得在电绝缘结构和导电结构之间形成气隙并且在导电结构和电绝缘结构上形成第二电绝缘层，使得第二电绝缘层跨越相邻的导电结构和电绝缘结构。

8. 发明申请

US20050079700A1 Strip conductor arrangement and method for producing a strip conductor arrangement 失效
标题翻译：带状导体布置及其制造方法
公开(公告)号：US20050079700A1
公开(公告)日：2005-04-14
申请号：US10487190
申请日：2002-08-09
申请人： Gunther Schindler , Werner Palmer , Zvonimir Gabric
发明人： Gunther Schindler , Werner Palmer , Zvonimir Gabric
IPC分类号： H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： An interconnect arrangement comprises a substrate made from a first insulating material with a substrate surface, at least two interconnects which are arranged next to one another in the substrate, a buffer layer made from a second insulating material above the substrate and comprising a buffer-layer surface, which is parallel to the substrate surface, at least one cavity, which is arranged between the interconnects and, with respect to the buffer-layer surface, extends deeper into the substrate than the interconnects, and a covering layer made from a third insulating material, which is arranged above the buffer layer and completely closes off the cavity with respect to the buffer-layer surface.
摘要翻译：互连装置包括由具有衬底表面的第一绝缘材料制成的衬底，在衬底中彼此相邻布置的至少两个互连件，由衬底上方的第二绝缘材料制成的缓冲层，并且包括缓冲层平行于衬底表面的表面，布置在互连件之间的至少一个空腔相对于缓冲层表面比互连件更深地延伸到衬底中，并且由第三绝缘体制成的覆盖层材料，其布置在缓冲层上方并相对于缓冲层表面完全封闭空腔。

9. 发明授权

US07211909B2 Monolithic integrated circuit arrangement 失效
标题翻译：单片集成电路布置
公开(公告)号：US07211909B2
公开(公告)日：2007-05-01
申请号：US10794588
申请日：2004-03-05
申请人： Gunther Schindler
发明人： Gunther Schindler
IPC分类号： H02K7/00 , H02K33/00 , H02K35/00 , H01H47/00 , H01F13/00
CPC分类号： H02K35/02
摘要： A monolithic integrated circuit arrangement containing a substrate, a functional unit formed in and/or on the substrate, and an energy supply unit, which is formed in and/or on the substrate and is coupled to the functional unit and has an inductance and a permanent magnet. The inductance and the permanent magnet are arranged such that, under a vibration on the circuit arrangement, the permanent magnet is moved relative to the inductance such that an electrical induced voltage for supplying the functional unit with electrical energy is induced by the inductance.
摘要翻译：一种单片集成电路装置，其包含衬底，形成在衬底中和/或衬底上的功能单元和能量供应单元，其形成在衬底中和/或衬底上并耦合到功能单元并具有电感和永久磁铁电感和永磁体被布置成使得在电路装置上的振动下，永磁体相对于电感移动，使得用于向功能单元提供电能的电感应电压由电感感应。

10. 发明申请

US20050195631A1 Method and apparatus for storing and reading information in a ferroelectric material 有权
标题翻译：用于在铁电材料中存储和读取信息的方法和装置
公开(公告)号：US20050195631A1
公开(公告)日：2005-09-08
申请号：US11034219
申请日：2005-01-13
申请人： Gunther Schindler , Markus Vogel , Christian Zybill
发明人： Gunther Schindler , Markus Vogel , Christian Zybill
IPC分类号： G11B9/00 , G11B9/02 , G11B11/00 , G11B11/16 , G11C11/22
CPC分类号： G11B9/1409 , B82Y10/00 , G11B9/02 , G11B9/14 , G11B9/1445 , G11B9/1463 , G11B11/007 , G11B11/16
摘要： To store information in a ferroelectric material, a sample probe is used to bring about mechanical action on individual domains and thereby to cause a reversal of polarization in the individual domains, with electrodes situated below the ferroelectric material being able to have a bias applied to them to stabilize the change/reversal of polarization. The reversal of polarization causes an alteration in the surface topography of the ferroelectric material, and this alteration can be used to read the information. The stored information is therefore obtained by ascertaining the surface topography of the ferroelectric material. The information is written and read using an AFM tip, with the tip being able to be operated in contact or tapping mode for the purpose of writing, and additionally in noncontact mode for the purpose of reading.
摘要翻译：为了将信息存储在铁电材料中，使用样本探针来对各个区域产生机械作用，从而导致各个区域中的极化反转，位于铁电材料下方的电极能够施加偏压以稳定极化的变化/反转。极化的反转导致铁电材料的表面形貌的变化，并且这种改变可以用于读取信息。因此，通过确定铁电材料的表面形貌来获得所存储的信息。使用AFM提示书写入和读取信息，为了写入目的，提示能够以接触或敲击模式操作，另外以非接触模式进行阅读。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式