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1. 发明申请

US20160118398A1 SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件，电子器件及其制造方法
公开(公告)号：US20160118398A1
公开(公告)日：2016-04-28
申请号：US14834454
申请日：2015-08-25
申请人： Gukhyon YON , Jaeyoung AHN , Bio KIM , Young-Jin NOH , Kwangmin PARK , Dongchul YOO
发明人： Gukhyon YON , Jaeyoung AHN , Bio KIM , Young-Jin NOH , Kwangmin PARK , Dongchul YOO
IPC分类号： H01L27/115 , H01L21/02 , H01L21/28 , H01L29/51 , H01L29/788
CPC分类号： H01L27/11582 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/28273 , H01L21/28282 , H01L27/11556 , H01L29/511 , H01L29/517 , H01L29/518 , H01L29/7926
摘要： Provided are a three dimensional semiconductor memory device and a method of fabricating the same. In the three dimensional semiconductor memory device, a stack of gate electrodes and insulating layers may be formed on a substrate, a channel structure may extend through the stack and connect to the substrate. A blocking insulating layer, a charge storing layer and a tunnel insulating layer may be formed between each gate electrode and the channel structure. The tunnel insulating layer may include a high-k dielectric layer with a low charge trap site density. The tunnel insulating layer may also include a first and a second tunnel insulating layers, and the high-k dielectric layer is provided between the first and second tunnel insulating layers.
摘要翻译：提供三维半导体存储器件及其制造方法。在三维半导体存储器件中，可以在衬底上形成一叠栅极电极和绝缘层，沟道结构可以延伸通过堆叠并连接至衬底。可以在每个栅电极和沟道结构之间形成阻挡绝缘层，电荷存储层和隧道绝缘层。隧道绝缘层可以包括具有低电荷陷阱位点密度的高k电介质层。隧道绝缘层还可以包括第一和第二隧道绝缘层，并且高k电介质层设置在第一和第二隧道绝缘层之间。

2. 发明申请

US20170287929A1 SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20170287929A1
公开(公告)日：2017-10-05
申请号：US15514239
申请日：2014-09-26
申请人： Sunggil KIM , Phil Ouk NAM , Gukhyon YON , Sunghae LEE , Woojin JANG , Dongchul YOO , Hunhyeong LIM , Junggeun JEE , Kihyun HWANG
发明人： Sunggil KIM , Phil Ouk NAM , Gukhyon YON , Sunghae LEE , Woojin JANG , Dongchul YOO , Hunhyeong LIM , Junggeun JEE , Kihyun HWANG
IPC分类号： H01L27/11582 , H01L21/02 , H01L21/28 , H01L21/311 , H01L27/1157 , H01L29/10
CPC分类号： H01L27/11582 , H01L21/0206 , H01L21/31116 , H01L27/115 , H01L27/1157 , H01L28/00 , H01L29/1037 , H01L29/40117
摘要： The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

3. 发明申请

US20160049423A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160049423A1
公开(公告)日：2016-02-18
申请号：US14695249
申请日：2015-04-24
申请人： Dongchul YOO , Chaeho KIM , Jaeyoung AHN , Woong LEE
发明人： Dongchul YOO , Chaeho KIM , Jaeyoung AHN , Woong LEE
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole.
摘要翻译：三维半导体器件可以包括包括单元阵列区域，字线接触区域和外围电路区域的基板，堆叠在基板上以从单元阵列区域延伸到字线接触区域的栅电极，通道穿透单元阵列区域上的栅电极并暴露基板的有源区域，穿过字线接触区域上的栅电极的裸孔，并暴露设置在基板上的器件隔离层，以及设置在基极上的半导体图案通道孔，但不在虚拟孔中。

4. 发明申请

US20160093634A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160093634A1
公开(公告)日：2016-03-31
申请号：US14865078
申请日：2015-09-25
申请人： Byong-hyun Jang , Dongchul YOO , Jaeyoung AHN , Hunhyeong LIM
发明人： Byong-hyun Jang , Dongchul YOO , Jaeyoung AHN , Hunhyeong LIM
IPC分类号： H01L27/115 , H01L29/49
CPC分类号： H01L29/495 , H01L27/11582
摘要： A three dimensional semiconductor memory device includes a vertical channel structure extending in a vertical direction on a substrate; interlayer insulating layers surrounding the vertical channel structure and being stacked in the vertical direction on the substrate, gate electrodes surrounding the vertical channel structure and being disposed between the interlayer insulating layers, corners of the gate electrodes adjacent to the vertical channel structure being rounded, and auxiliary gate insulating patterns disposed between the gate electrodes and the vertical channel structure, wherein a side surface of the auxiliary gate insulating pattern is substantially coplanar with a side surface of the interlayer insulating layer in the vertical direction on the substrate.
摘要翻译：三维半导体存储器件包括在衬底上沿垂直方向延伸的垂直沟道结构; 围绕垂直沟道结构并在垂直方向上堆叠在衬底上的层间绝缘层，围绕垂直沟道结构的栅极，并且设置在层间绝缘层之间，与垂直沟道结构相邻的栅电极的拐角被倒圆，以及辅助栅极绝缘图案，设置在栅电极和垂直沟道结构之间，其中辅助栅极绝缘图案的侧表面与衬底上的垂直方向上的层间绝缘层的侧表面大致共面。

5. 发明申请

US20140070302A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20140070302A1
公开(公告)日：2014-03-13
申请号：US13974122
申请日：2013-08-23
申请人： Dongchul YOO , Phil Ouk NAM , Junkyu YANG , Woong LEE , Woosung LEE , JinGyun KIM , Daehong EOM
发明人： Dongchul YOO , Phil Ouk NAM , Junkyu YANG , Woong LEE , Woosung LEE , JinGyun KIM , Daehong EOM
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/04 , H01L29/1037 , H01L29/42356 , H01L29/4236 , H01L29/42364 , H01L29/511 , H01L29/7926
摘要： A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.
摘要翻译：一种三维（3D）半导体存储器件及其制造方法，该器件包括堆叠在衬底上的绝缘层; 绝缘层之间的水平结构，分别包括栅电极的水平结构; 垂直结构分别穿透绝缘层和水平结构，垂直结构分别包括半导体柱; 和外延图案，每个外延图案在衬底和每个垂直结构之间，其中外延图案的最小宽度小于垂直结构中对应的一个的宽度。

6. 发明申请

US20150279857A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150279857A1
公开(公告)日：2015-10-01
申请号：US14539140
申请日：2014-11-12
申请人： Jung-Hwan KIM , Hanvit YANG , Jintae NOH , Dongchul YOO
发明人： Jung-Hwan KIM , Hanvit YANG , Jintae NOH , Dongchul YOO
IPC分类号： H01L27/115 , H01L23/00
CPC分类号： H01L27/11582
摘要： Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. A first vertical channel pattern is disposed in a lower portion of each vertical channel structure. A gate oxide layer is formed on a sidewall of the first vertical channel pattern. A recess region is formed in the substrate between the vertical channel structures. A buffer oxide layer is formed in the recess region. An oxidation inhibiting layer is provided in the substrate to surround the recess region. The oxidation inhibiting layer is in contact with the buffer oxide layer and inhibits growth of the buffer oxide layer.
摘要翻译：本发明的概念提供半导体存储器件及其制造方法。堆叠结构和垂直通道结构设置在基板上。堆叠结构包括在基板上交替重复堆叠的绝缘层和栅电极。第一垂直通道图案设置在每个垂直通道结构的下部。栅极氧化层形成在第一垂直沟道图案的侧壁上。在垂直通道结构之间的衬底中形成凹陷区域。在凹陷区域中形成缓冲氧化物层。在基板中设置氧化抑制层以包围凹部。氧化抑制层与缓冲氧化物层接触并抑制缓冲氧化物层的生长。

7. 发明申请

US20170133400A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20170133400A1
公开(公告)日：2017-05-11
申请号：US15414345
申请日：2017-01-24
申请人： Dongchul YOO , Phil Ouk NAM , Junkyu YANG , Woong LEE , Woosung LEE , JinGyun KIM , Daehong EOM
发明人： Dongchul YOO , Phil Ouk NAM , Junkyu YANG , Woong LEE , Woosung LEE , JinGyun KIM , Daehong EOM
IPC分类号： H01L27/11582 , H01L29/04 , H01L29/10 , H01L27/1157 , H01L29/423
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/04 , H01L29/1037 , H01L29/42356 , H01L29/4236 , H01L29/42364 , H01L29/511 , H01L29/7926
摘要： A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

8. 发明申请

US20150311214A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：三维半导体存储器件
公开(公告)号：US20150311214A1
公开(公告)日：2015-10-29
申请号：US14790969
申请日：2015-07-02
申请人： Dongchul YOO , Phil Ouk NAM , Junkyu YANG , Woong LEE , Woosung LEE , JinGyun KIM , Daehong EOM
发明人： Dongchul YOO , Phil Ouk NAM , Junkyu YANG , Woong LEE , Woosung LEE , JinGyun KIM , Daehong EOM
IPC分类号： H01L27/115 , H01L29/423
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/04 , H01L29/1037 , H01L29/42356 , H01L29/4236 , H01L29/42364 , H01L29/511 , H01L29/7926
摘要： A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.
摘要翻译：一种三维（3D）半导体存储器件及其制造方法，该器件包括堆叠在衬底上的绝缘层; 绝缘层之间的水平结构，分别包括栅电极的水平结构; 垂直结构分别穿透绝缘层和水平结构，垂直结构分别包括半导体柱; 和外延图案，每个外延图案在衬底和每个垂直结构之间，其中外延图案的最小宽度小于垂直结构中对应的一个的宽度。

9. 发明申请

US20120300474A1 LIGHTING APPARATUS 有权
标题翻译：照明设备
公开(公告)号：US20120300474A1
公开(公告)日：2012-11-29
申请号：US13312012
申请日：2011-12-06
申请人： Byungsang JUNG , Sejoon YOU , Kyungtaek LEE , Hyunha KIM , Seoyoung MAENG , Dongchul YOO
发明人： Byungsang JUNG , Sejoon YOU , Kyungtaek LEE , Hyunha KIM , Seoyoung MAENG , Dongchul YOO
IPC分类号： F21V29/02
CPC分类号： F21K9/13 , F21K9/23 , F21V29/507 , F21V29/63 , F21V29/773 , F21Y2103/33 , F21Y2115/10 , H01L2224/48091 , H01L2224/48464 , H01L2224/73265 , H01L2924/00014
摘要： A lighting apparatus can dissipate heat by conduction and convection. A heat sink is provided with an active cooling device for the lighting apparatus.
摘要翻译：照明装置可以通过传导和对流散热。散热器设置有用于照明装置的主动冷却装置。

10. 发明申请

US20120135583A1 METHODS OF MANUFACTURING THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES USING SUB-PLATES 有权
标题翻译：使用子板制造三维半导体存储器件的方法
公开(公告)号：US20120135583A1
公开(公告)日：2012-05-31
申请号：US13284435
申请日：2011-10-28
申请人： Byong-hyun JANG , Dongchul YOO , Chanjin PARK , Hanmei CHOI
发明人： Byong-hyun JANG , Dongchul YOO , Chanjin PARK , Hanmei CHOI
IPC分类号： H01L21/762 , H01L21/60 , H01L21/336
CPC分类号： H01L21/762 , H01L21/76224 , H01L27/1157 , H01L27/11582
摘要： A method of manufacturing a Three Dimensional (3D) semiconductor memory device can be provided by forming at least one trench in a plate stack structure to divide the plate stack structure into a plurality of sub-plate stack structures between forming a plurality of vertical active patterns in the plate stack structure and forming pads of a stepped structure from the plate stack structure.
摘要翻译：可以通过在板堆叠结构中形成至少一个沟槽来形成制造三维（3D）半导体存储器件的方法，以在形成多个垂直有源图案之间将板堆叠结构分成多个子板堆叠结构在板堆叠结构中和从板堆叠结构的阶梯结构的成形垫。

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