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1. 发明授权

US08828865B2 Method of forming metal interconnections of semiconductor device 有权
标题翻译：形成半导体器件金属互连的方法
公开(公告)号：US08828865B2
公开(公告)日：2014-09-09
申请号：US13431446
申请日：2012-03-27
申请人： WooJin Jang , KyoungWoo Lee
发明人： WooJin Jang , KyoungWoo Lee
IPC分类号： H01L21/44 , H01L21/768 , H01L23/48
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L23/53228 , H01L2224/13
摘要： A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening; forming a barrier metal pattern conformally covering a bottom surface and an inner sidewall of the opening; forming a metal pattern exposing a part of the inner sidewall of the barrier metal pattern in the opening; forming a metal capping layer on the top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process, wherein the thickness of the metal capping layer on the metal pattern is greater than the thickness of the metal capping layer on the low-k dielectric layer; and forming a metal capping pattern covering the top surface of the metal pattern by planarizing the metal capping layer down to the top surface of the low-k dielectric layer.
摘要翻译：提供一种形成半导体器件的金属互连的方法。该方法包括形成包括开口的低k电介质层; 形成保形地覆盖所述开口的底部表面和内侧壁的阻挡金属图案; 形成露出所述开口中的所述阻挡金属图案的内侧壁的一部分的金属图案; 使用选择性化学气相沉积工艺在金属图案和低k电介质层的顶表面上形成金属覆盖层，其中金属图案上的金属覆盖层的厚度大于金属覆盖层的厚度在低k电介质层上; 以及通过将金属覆盖层平坦化到低k电介质层的顶表面来形成覆盖金属图案的顶表面的金属覆盖图案。

2. 发明申请

US20120252208A1 METHOD OF FORMING METAL INTERCONNECTIONS OF SEMICONDUCTOR DEVICE 有权
标题翻译：形成金属互连的半导体器件的方法
公开(公告)号：US20120252208A1
公开(公告)日：2012-10-04
申请号：US13431446
申请日：2012-03-27
申请人： WooJin Jang , KyoungWoo Lee
发明人： WooJin Jang , KyoungWoo Lee
IPC分类号： H01L21/768
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L23/53228 , H01L2224/13
摘要： A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening; forming a barrier metal pattern conformally covering a bottom surface and an inner sidewall of the opening; forming a metal pattern exposing a part of the inner sidewall of the barrier metal pattern in the opening; forming a metal capping layer on the top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process, wherein the thickness of the metal capping layer on the metal pattern is greater than the thickness of the metal capping layer on the low-k dielectric layer; and forming a metal capping pattern covering the top surface of the metal pattern by planarizing the metal capping layer down to the top surface of the low-k dielectric layer.
摘要翻译：提供一种形成半导体器件的金属互连的方法。该方法包括形成包括开口的低k电介质层; 形成保形地覆盖所述开口的底部表面和内侧壁的阻挡金属图案; 形成露出所述开口中的所述阻挡金属图案的内侧壁的一部分的金属图案; 使用选择性化学气相沉积工艺在金属图案和低k电介质层的顶表面上形成金属覆盖层，其中金属图案上的金属覆盖层的厚度大于金属覆盖层的厚度在低k电介质层上; 以及通过将金属覆盖层平坦化到低k电介质层的顶表面来形成覆盖金属图案的顶表面的金属覆盖图案。

3. 发明申请

US20170287929A1 SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20170287929A1
公开(公告)日：2017-10-05
申请号：US15514239
申请日：2014-09-26
申请人： Sunggil KIM , Phil Ouk NAM , Gukhyon YON , Sunghae LEE , Woojin JANG , Dongchul YOO , Hunhyeong LIM , Junggeun JEE , Kihyun HWANG
发明人： Sunggil KIM , Phil Ouk NAM , Gukhyon YON , Sunghae LEE , Woojin JANG , Dongchul YOO , Hunhyeong LIM , Junggeun JEE , Kihyun HWANG
IPC分类号： H01L27/11582 , H01L21/02 , H01L21/28 , H01L21/311 , H01L27/1157 , H01L29/10
CPC分类号： H01L27/11582 , H01L21/0206 , H01L21/31116 , H01L27/115 , H01L27/1157 , H01L28/00 , H01L29/1037 , H01L29/40117
摘要： The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

4. 发明授权

US10685972B2 Semiconductor memory devices and methods for fabricating the same 有权
公开(公告)号：US10685972B2
公开(公告)日：2020-06-16
申请号：US15514239
申请日：2014-09-26
申请人： Sunggil Kim , Phil Ouk Nam , Gukhyon Yon , Sunghae Lee , Woojin Jang , Dongchul Yoo , Hunhyeong Lim , Junggeun Jee , Kihyun Hwang
发明人： Sunggil Kim , Phil Ouk Nam , Gukhyon Yon , Sunghae Lee , Woojin Jang , Dongchul Yoo , Hunhyeong Lim , Junggeun Jee , Kihyun Hwang
IPC分类号： H01L27/11582 , H01L27/11568 , H01L21/28 , H01L27/115 , H01L49/02 , H01L21/02 , H01L21/311 , H01L27/1157 , H01L29/10
摘要： The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

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