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1. 发明授权

US08572355B2 Support for non-local returns in parallel thread SIMD engine 有权
标题翻译：支持并行线程SIMD引擎中的非本地返回
公开(公告)号：US08572355B2
公开(公告)日：2013-10-29
申请号：US12881065
申请日：2010-09-13
申请人： Guillermo Juan Rozas , Brett W. Coon
发明人： Guillermo Juan Rozas , Brett W. Coon
IPC分类号： G06F9/30
CPC分类号： G06F9/30058 , G06F9/3851
摘要： One embodiment of the present invention sets forth a method for executing a non-local return instruction in a parallel thread processor. The method comprises the steps of receiving, within the thread group, a first long jump instruction and, in response, popping a first token from the execution stack. The method also comprises determining whether the first token is a first long jump token that was pushed onto the execution stack when a first push instruction associated with the first long jump instruction was executed, and when the first token is the first long jump token, jumping to the second instruction based on the address specified by the first long jump token, or, when the first token is not the first long jump token, disabling the active thread until the first long jump token is popped from the execution stack.
摘要翻译：本发明的一个实施例提出了一种用于在并行线程处理器中执行非本地返回指令的方法。该方法包括以下步骤：在线程组内接收第一长跳转指令，作为响应，从执行堆栈中弹出第一个令牌。该方法还包括当与第一长跳转指令相关联的第一推送指令被执行时，确定第一令牌是否是被推送到执行堆栈上的第一长跳转令牌，以及当第一令牌是第一长跳转令牌时，跳转基于由第一长跳转令牌指定的地址到第二指令，或者当第一令牌不是第一长跳转令牌时，禁用活动线程，直到从执行堆栈弹出第一个长跳转令牌。

2. 发明申请

US20110078418A1 Support for Non-Local Returns in Parallel Thread SIMD Engine 有权
标题翻译：支持并行线程SIMD引擎中的非本地返回
公开(公告)号：US20110078418A1
公开(公告)日：2011-03-31
申请号：US12881065
申请日：2010-09-13
申请人： Guillermo Juan Rozas , Brett W. Coon
发明人： Guillermo Juan Rozas , Brett W. Coon
IPC分类号： G06F9/38
CPC分类号： G06F9/30058 , G06F9/3851
摘要： One embodiment of the present invention sets forth a method for executing a non-local return instruction in a parallel thread processor. The method comprises the steps of receiving, within the thread group, a first long jump instruction and, in response, popping a first token from the execution stack. The method also comprises determining whether the first token is a first long jump token that was pushed onto the execution stack when a first push instruction associated with the first long jump instruction was executed, and when the first token is the first long jump token, jumping to the second instruction based on the address specified by the first long jump token, or, when the first token is not the first long jump token, disabling the active thread until the first long jump token is popped from the execution stack.
摘要翻译：本发明的一个实施例提出了一种用于在并行线程处理器中执行非本地返回指令的方法。该方法包括以下步骤：在线程组内接收第一长跳转指令，作为响应，从执行堆栈中弹出第一个令牌。该方法还包括当与第一长跳转指令相关联的第一推送指令被执行时，确定第一令牌是否是被推送到执行堆栈上的第一长跳转令牌，以及当第一令牌是第一长跳转令牌时，跳转基于由第一长跳转令牌指定的地址到第二指令，或者当第一令牌不是第一长跳转令牌时，禁用活动线程，直到从执行堆栈弹出第一个长跳转令牌。

3. 发明授权

US09639479B2 Instructions for managing a parallel cache hierarchy 有权
公开(公告)号：US09639479B2
公开(公告)日：2017-05-02
申请号：US12888409
申请日：2010-09-22
申请人： John R. Nickolls , Brett W. Coon , Michael C. Shebanow
发明人： John R. Nickolls , Brett W. Coon , Michael C. Shebanow
IPC分类号： G06F12/121 , G06F12/0811 , G06F12/0862 , G06F9/30
CPC分类号： G06F9/3887 , G06F9/30043 , G06F9/3009 , G06F9/3836 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/121 , G06F2212/452
摘要： A method for managing a parallel cache hierarchy in a processing unit. The method includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.

4. 发明授权

US09189242B2 Credit-based streaming multiprocessor warp scheduling 有权
标题翻译：基于信用流的多处理器扭曲调度
公开(公告)号：US09189242B2
公开(公告)日：2015-11-17
申请号：US12885299
申请日：2010-09-17
申请人： John Erik Lindholm , Brett W. Coon , Jered Wierzbicki , Robert J. Stoll , Stuart F. Oberman
发明人： John Erik Lindholm , Brett W. Coon , Jered Wierzbicki , Robert J. Stoll , Stuart F. Oberman
IPC分类号： G06F9/50 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： One embodiment of the present invention sets forth a technique for ensuring cache access instructions are scheduled for execution in a multi-threaded system to improve cache locality and system performance. A credit-based technique may be used to control instruction by instruction scheduling for each warp in a group so that the group of warps is processed uniformly. A credit is computed for each warp and the credit contributes to a weight for each warp. The weight is used to select instructions for the warps that are issued for execution.
摘要翻译：本发明的一个实施例提出了一种用于确保高速缓存访问指令被调度用于在多线程系统中执行以提高高速缓存位置和系统性能的技术。可以使用基于信用的技术来对组中的每个翘曲的指令调度来控制指令，使得一组经线被均匀地处理。对每个经纱计算信用额度，并且信用额度有助于每个经线的权重。权重用于选择要执行的经纱的说明。

5. 发明授权

US08405665B2 Programmable graphics processor for multithreaded execution of programs 有权
标题翻译：用于多线程执行程序的可编程图形处理器
公开(公告)号：US08405665B2
公开(公告)日：2013-03-26
申请号：US13466043
申请日：2012-05-07
申请人： John Erik Lindholm , Brett W. Coon , Stuart F. Oberman , Ming Y. Siu , Matthew P. Gerlach
发明人： John Erik Lindholm , Brett W. Coon , Stuart F. Oberman , Ming Y. Siu , Matthew P. Gerlach
IPC分类号： G06F15/16 , G06F15/80 , G06F13/14 , G06T1/20
CPC分类号： G06T15/005
摘要： A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.
摘要翻译：处理单元包括多个执行流水线，每个执行流水线连接到第一输入部分，用于接收用于像素处理的输入数据和用于接收用于顶点处理的输入数据的第二输入部分和用于存储经处理的像素数据的第一输出部分和用于存储经处理的顶点数据的第二输出部分。经处理的顶点数据被光栅化并扫描转换为用作像素处理的输入数据的像素数据。经处理的像素数据被输出到光栅分析器。

6. 发明申请

US20120221808A1 SHARED SINGLE-ACCESS MEMORY WITH MANAGEMENT OF MULTIPLE PARALLEL REQUESTS 有权
标题翻译：具有多个并行请求管理的共享单访存储器
公开(公告)号：US20120221808A1
公开(公告)日：2012-08-30
申请号：US13466057
申请日：2012-05-07
申请人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
发明人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , Y02D10/13
摘要： A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.
摘要翻译：多线程处理器中的并发线程使用内存。任何可寻址的存储位置都可以由任何并发线程访问，但一次只能访问一个位置。存储器耦合到并行处理引擎，其产生一组并行存储器访问请求，每个指定对于不同请求可能相同或不同的目标地址。序列化逻辑选择一个目标地址，并确定哪个请求指定所选择的目标地址。允许所有这些请求并行进行，而其他请求被推迟。可以通过序列化逻辑重新生成和处理延迟请求，以便通过一次访问组中的每个不同的目标地址来满足一组请求。

7. 发明授权

US08225076B1 Scoreboard having size indicators for tracking sequential destination register usage in a multi-threaded processor 有权
标题翻译：记分牌具有用于跟踪多线程处理器中的顺序目的地寄存器使用的大小指示符
公开(公告)号：US08225076B1
公开(公告)日：2012-07-17
申请号：US12233515
申请日：2008-09-18
申请人： Brett W. Coon , Peter C. Mills , Stuart F. Oberman , Ming Y. Siu
发明人： Brett W. Coon , Peter C. Mills , Stuart F. Oberman , Ming Y. Siu
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3838 , G06F9/3879 , G06F9/3885
摘要： A scoreboard memory for a processing unit has separate memory regions allocated to each of the multiple threads to be processed. For each thread, the scoreboard memory stores register identifiers of registers that have pending writes. When an instruction is added to an instruction buffer, the register identifiers of the registers specified in the instruction are compared with the register identifiers stored in the scoreboard memory for that instruction's thread, and a multi-bit value representing the comparison result is generated. The multi-bit value is stored with the instruction in the instruction buffer and may be updated as instructions belonging to the same thread complete their execution. Before the instruction is issued for execution, this multi-bit value is checked. If this multi-bit value indicates that none of the registers specified in the instruction have pending writes, the instruction is allowed to issue for execution.
摘要翻译：用于处理单元的记分板存储器具有分配给要处理的多个线程中的每一个的分离的存储器区域。对于每个线程，记分板存储器存储具有待处理写入的寄存器的寄存器标识符。当指令被添加到指令缓冲器中时，将指令中指定的寄存器的寄存器标识符与存储在该指令的线程的记分板存储器中的寄存器标识进行比较，并生成表示比较结果的多位值。多位值与指令一起存储在指令缓冲器中，并且可以更新为属于同一线程的指令完成其执行。在执行指令之前，将检查该多位值。如果该多位值表示指令中没有指定的寄存器没有挂起写操作，则允许指令执行。

8. 发明授权

US08176265B2 Shared single-access memory with management of multiple parallel requests 有权
标题翻译：具有管理多个并行请求的共享单访问存储器
公开(公告)号：US08176265B2
公开(公告)日：2012-05-08
申请号：US13165638
申请日：2011-06-21
申请人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
发明人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , Y02D10/13
摘要： A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.
摘要翻译：多线程处理器中的并发线程使用内存。任何可寻址的存储位置都可以由任何并发线程访问，但一次只能访问一个位置。存储器耦合到并行处理引擎，其产生一组并行存储器访问请求，每个指定对于不同请求可能相同或不同的目标地址。序列化逻辑选择一个目标地址，并确定哪个请求指定所选择的目标地址。允许所有这些请求并行进行，而其他请求被推迟。可以通过序列化逻辑重新生成和处理延迟请求，以便通过一次访问组中的每个不同的目标地址来满足一组请求。

9. 发明申请

US20120026175A1 HIERARCHICAL PROCESSOR ARRAY 有权
标题翻译：分层处理器阵列
公开(公告)号：US20120026175A1
公开(公告)日：2012-02-02
申请号：US13270215
申请日：2011-10-10
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件多种图形操作与不同阶段的图形处理相关联。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

10. 发明授权

US08108625B1 Shared memory with parallel access and access conflict resolution mechanism 有权
标题翻译：共享内存具有并行访问和访问冲突解决机制
公开(公告)号：US08108625B1
公开(公告)日：2012-01-31
申请号：US11554546
申请日：2006-10-30
申请人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
发明人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
IPC分类号： G06F12/00
CPC分类号： G06F13/1663
摘要： Concurrent threads in a multithreaded processor share access to a memory, with any location in the shared memory being accessible by any thread. In one embodiment, the shared memory has multiple independently-addressable memory banks, and one location per bank can be accessed in parallel. Parallel processing engines executing the threads generate a group of parallel memory access requests. Address conflict logic determines whether the requests can be satisfied in parallel (e.g., based on bank access constraints) and serializes the requests to the extent needed to avoid conflicts. In some embodiments, data read from one address in the shared memory can be broadcast to multiple processing engines.
摘要翻译：多线程处理器中的并发线程共享对内存的访问，任何线程都可以访问共享内存中的任何位置。在一个实施例中，共享存储器具有多个可独立寻址的存储体，并且可以并行地访问每个存储体的一个位置。执行线程的并行处理引擎生成一组并行内存访问请求。地址冲突逻辑确定请求是否可以并行满足（例如，基于银行访问约束），并将请求序列化到避免冲突所需的程度。在一些实施例中，从共享存储器中的一个地址读取的数据可以广播到多个处理引擎。

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