专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20150003181A1 POWER MANAGEMENT IN MULTI-DIE ASSEMBLIES 有权
标题翻译：多模组件电源管理
公开(公告)号：US20150003181A1
公开(公告)日：2015-01-01
申请号：US13927227
申请日：2013-06-26
申请人： Guido Droege , Andre Schaefer , Uwe Zillmann
发明人： Guido Droege , Andre Schaefer , Uwe Zillmann
IPC分类号： G11C5/14
CPC分类号： H02J1/00 , G05F1/618 , G11C5/025 , G11C5/14 , G11C5/147 , G11C7/00 , H01L2924/19042 , H01L2924/19104 , H02M1/088
摘要： An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.
摘要翻译：诸如异种装置的装置至少包括第一模具和第二模具。该装置还包括第一电感元件，第二电感元件和开关控制电路。开关控制电路设置在第一管芯中。开关控制电路控制通过第一电感元件的电流以产生第一电压。第一个电压为第一个模具供电。第二电感元件耦合到第一电感元件。第二电感元件产生第二电压以对第二管芯供电。第一模具和第二模具可以根据不同的技术制造，并且其中第一模具和第二模具耐受不同的最大电压。第一电压的大小可以大于第二电压的幅度。

2. 发明申请

US20080002801A1 Fast-settling clock generator 审中-公开
标题翻译：快速建立时钟发生器
公开(公告)号：US20080002801A1
公开(公告)日：2008-01-03
申请号：US11478268
申请日：2006-06-29
申请人： Guido Droege , Uwe Zillmann
发明人： Guido Droege , Uwe Zillmann
IPC分类号： H03D3/24
CPC分类号： H03D13/002 , H03L1/026 , H03L7/089 , H03L7/10 , H03L7/18
摘要： A clock generator with a fast settling time features a coarse-tuning circuit that is executed a single time, and a fine-tuning circuit that is executed periodically. The fine-tuning circuit sends an analog voltage to a voltage-controlled oscillator (VCO). The coarse-tuning circuit sends a load capacitance parameter to the VCO. The analog voltage and the load capacitance are used to program the VCO, which generates a clock signal. The coarse-tuning circuit and the fine-tuning circuit include registers that store the load capacitance and analog voltage information, respectively, in digital form. When switching of the oscillator occurs, the clock generator quickly produces a clock signal in accordance with the stored digital values.
摘要翻译：具有快速建立时间的时钟发生器具有单次执行的粗调电路和周期性执行的微调电路。微调电路将模拟电压发送到压控振荡器（VCO）。粗调电路向VCO发送负载电容参数。模拟电压和负载电容用于对产生时钟信号的VCO进行编程。粗调电路和微调电路分别包含以数字形式存储负载电容和模拟电压信息的寄存器。当振荡器发生切换时，时钟发生器根据存储的数字值快速产生时钟信号。

3. 发明授权

US09000577B2 Interlayer communications for 3D integrated circuit stack 有权
标题翻译： 3D集成电路堆栈的层间通信
公开(公告)号：US09000577B2
公开(公告)日：2015-04-07
申请号：US13976562
申请日：2011-09-30
申请人： Guido Droege , Niklas Linkewitsch , Andre Schaefer
发明人： Guido Droege , Niklas Linkewitsch , Andre Schaefer
IPC分类号： H01L23/02 , H01L23/522 , H01L25/065 , H01L23/64 , H01L23/48
CPC分类号： H01L25/0657 , G11C5/04 , G11C5/063 , G11C7/1057 , G11C7/1084 , H01L23/481 , H01L23/5223 , H01L23/642 , H01L2223/6622 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544
摘要： Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.
摘要翻译：一些实施例为3D堆叠模块提供电容AC耦合层间通信。

4. 发明申请

US20130293292A1 INTERLAYER COMMUNICATIONS FOR 3D INTEGRATED CIRCUIT STACK 有权
公开(公告)号：US20130293292A1
公开(公告)日：2013-11-07
申请号：US13976562
申请日：2011-09-30
申请人： Guido Droege , Niklas Linkewitsch , Andre Schaefer
发明人： Guido Droege , Niklas Linkewitsch , Andre Schaefer
IPC分类号： H01L23/522
CPC分类号： H01L25/0657 , G11C5/04 , G11C5/063 , G11C7/1057 , G11C7/1084 , H01L23/481 , H01L23/5223 , H01L23/642 , H01L2223/6622 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544
摘要： Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式