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1. 发明申请

US20140379960A1 BACKGROUND REORDERING - A PREVENTIVE WEAR-OUT CONTROL MECHANISM WITH LIMITED OVERHEAD 有权
标题翻译：背景技术 - 具有限制性的预防性磨损控制机制
公开(公告)号：US20140379960A1
公开(公告)日：2014-12-25
申请号：US13991338
申请日：2011-12-05
申请人： Niklas Linkewitsch
发明人： Niklas Linkewitsch
IPC分类号： G06F12/02 , G06F3/06
CPC分类号： G06F12/0246 , G06F3/0619 , G06F3/0638 , G06F3/065 , G06F3/0679 , G06F2212/7211
摘要： Embodiments of the present disclosure describe background reordering techniques and configurations to prevent wear-out of an integrated circuit device such as a memory device. In one embodiment, a method includes receiving information about one or more incoming access transactions to a memory device from a processor, determining that a wear-leveling operation is to be performed based on a cumulative number of access transactions to the memory device, the cumulative number of access transactions including the one or more incoming access transactions, and performing the wear-leveling operation by mapping a first physical address of the memory device to a second physical address of the memory device based on a pseudo-random mapping function, and copying information from the first physical address to the second physical address. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了用于防止诸如存储器设备的集成电路设备的磨损的背景重排序技术和配置。在一个实施例中，一种方法包括从处理器接收关于存储器设备的一个或多个传入访问事务的信息，基于对存储器设备的访问事务的累积次数确定要执行损耗均衡操作，累积访问事务的数量，包括一个或多个传入访问事务，以及通过基于伪随机映射函数将存储器件的第一物理地址映射到存储器件的第二物理地址来执行损耗均衡操作，并且复制从第一个物理地址到第二个物理地址的信息。可以描述和/或要求保护其他实施例。

2. 发明授权

US07564875B2 Techniques to map and de-map signals 失效
标题翻译：映射和解映射信号的技术
公开(公告)号：US07564875B2
公开(公告)日：2009-07-21
申请号：US10706356
申请日：2003-11-11
申请人： Niklas Linkewitsch , Michael Kauschke
发明人： Niklas Linkewitsch , Michael Kauschke
IPC分类号： H04J3/07
CPC分类号： H04J3/167 , H04J3/0685 , H04J3/07 , H04J3/1611 , H04L12/66
摘要： Briefly, a system that maps SONET/SDH data to an OTN frame using justification commands. Briefly, a system that de-maps an OTN frame into SONET/SDH data using justification commands.
摘要翻译：简而言之，使用调整命令将SONET / SDH数据映射到OTN帧的系统。简而言之，使用调整命令将OTN帧解映射成SONET / SDH数据的系统。

3. 发明授权

US09000577B2 Interlayer communications for 3D integrated circuit stack 有权
标题翻译： 3D集成电路堆栈的层间通信
公开(公告)号：US09000577B2
公开(公告)日：2015-04-07
申请号：US13976562
申请日：2011-09-30
申请人： Guido Droege , Niklas Linkewitsch , Andre Schaefer
发明人： Guido Droege , Niklas Linkewitsch , Andre Schaefer
IPC分类号： H01L23/02 , H01L23/522 , H01L25/065 , H01L23/64 , H01L23/48
CPC分类号： H01L25/0657 , G11C5/04 , G11C5/063 , G11C7/1057 , G11C7/1084 , H01L23/481 , H01L23/5223 , H01L23/642 , H01L2223/6622 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544
摘要： Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.
摘要翻译：一些实施例为3D堆叠模块提供电容AC耦合层间通信。

4. 发明授权

US07215685B2 Frame aligning deframer 有权
标题翻译：镜框对齐除镜
公开(公告)号：US07215685B2
公开(公告)日：2007-05-08
申请号：US10091134
申请日：2002-03-04
申请人： Niklas Linkewitsch
发明人： Niklas Linkewitsch
IPC分类号： H04J3/06
CPC分类号： H04J3/0608
摘要： A method is disclosed of aligning a frame in a digital communication system. The method includes comparing a portion of a received data sequence to a portion of a predetermined sequence. If the total number of comparison errors does not exceed a tolerance threshold that is greater than zero then the frame is aligned.
摘要翻译：公开了一种在数字通信系统中对准帧的方法。该方法包括将接收的数据序列的一部分与预定序列的一部分进行比较。如果比较错误的总数不超过大于零的公差阈值，则帧对齐。

5. 发明申请

US20120137196A1 FORWARD ERROR CORRECTION MAPPING AND DE-MAPPING TECHNIQUES 有权
标题翻译：前向错误校正映射和去映射技术
公开(公告)号：US20120137196A1
公开(公告)日：2012-05-31
申请号：US13365295
申请日：2012-02-03
申请人： Niklas Linkewitsch
发明人： Niklas Linkewitsch
IPC分类号： H03M13/05 , G06F11/10 , H03M13/07
CPC分类号： H04L1/005 , H03M13/2909 , H04J3/0605 , H04L1/0041 , H04L1/0057
摘要： Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.
摘要翻译：简而言之，提供不同级别的增强的前向纠错而不修改帧的线速率的技术。

6. 发明申请

US20080240021A1 MAC coordination architecture for multi-ratio coexistence and a method for connecting over sideband channels 审中-公开
标题翻译：用于多比率共存的MAC协调架构和用于连接边带通道的方法
公开(公告)号：US20080240021A1
公开(公告)日：2008-10-02
申请号：US11731540
申请日：2007-03-29
申请人： Xingang Guo , Changwen Liu , Srikant Kuppa , Hsin-Yuo Liu , Niklas Linkewitsch , Reed D. Vilhauer
发明人： Xingang Guo , Changwen Liu , Srikant Kuppa , Hsin-Yuo Liu , Niklas Linkewitsch , Reed D. Vilhauer
IPC分类号： H04Q7/00
CPC分类号： H04W72/1215 , H04W88/06 , H04W88/10
摘要： A wireless device with a multi-radio platform includes a scheduling coordinator connected by a control bus to enable the radios to share frequency spectrum by operating during time slots requested by the radios, avoid collisions, mitigate interference and control shared hardware components.
摘要翻译：具有多无线电平台的无线设备包括由控制总线连接的调度协调器，以使得无线电设备能够通过在由无线电设备请求的时隙内进行操作来共享频谱，避免冲突，减轻干扰并控制共享的硬件组件。

7. 发明申请

US20050053285A1 Forward error correction mapping and de-mapping techniques 有权
标题翻译：前向纠错映射和去映射技术
公开(公告)号：US20050053285A1
公开(公告)日：2005-03-10
申请号：US10660404
申请日：2003-09-10
申请人： Niklas Linkewitsch
发明人： Niklas Linkewitsch
IPC分类号： H03M13/29 , H04J3/06 , H04J3/16 , H04L1/00 , G06K9/36
CPC分类号： H04L1/005 , H03M13/2909 , H04J3/0605 , H04L1/0041 , H04L1/0057
摘要： Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.
摘要翻译：简而言之，提供不同级别的增强的前向纠错而不修改帧的线速率的技术。

8. 发明申请

US20160203085A1 CACHE OPERATIONS FOR MEMORY MANAGEMENT 有权
标题翻译：内存管理的高速缓存操作
公开(公告)号：US20160203085A1
公开(公告)日：2016-07-14
申请号：US14127483
申请日：2013-09-27
申请人： Tim KRANICH , Matthias GRIES , Niklas LINKEWITSCH
发明人： Tim KRANICH , Matthias GRIES , Niklas LINKEWITSCH
IPC分类号： G06F12/08 , G06F12/12 , G06F12/10 , G06F9/44
CPC分类号： G06F12/0891 , G06F9/4406 , G06F12/0238 , G06F12/0246 , G06F12/0802 , G06F12/0848 , G06F12/0877 , G06F12/0893 , G06F12/1054 , G06F12/12 , G06F12/126 , G06F2212/1016 , G06F2212/1021 , G06F2212/1032 , G06F2212/60 , G06F2212/7201 , G06F2212/7203 , G06F2212/7211 , Y02D10/13
摘要： In accordance with the present description, cache operations for a memory-sided cache in front of a backing memory such as a byte-addressable non-volatile memory, include combining at least two of a first operation, a second operation and a third operation, wherein the first operation includes evicting victim cache entries from the cache memory in accordance with a replacement policy which is biased to evict cache entries having clean cache lines over evicting cache entries having dirty cache lines. The second operation includes evicting victim cache entries from the primary cache memory to a victim cache memory of the cache memory, and the third operation includes translating memory location addresses to shuffle and spread the memory location addresses within an address range of the backing memory. It is believed that various combinations of these operations may provide improved operation of a memory. Other aspects are described herein.
摘要翻译：根据本说明书，在诸如字节可寻址非易失性存储器的后备存储器之前的存储器侧高速缓存的高速缓存操作包括组合第一操作，第二操作和第三操作中的至少两个，其中所述第一操作包括根据替代策略来驱逐来自所述高速缓冲存储器的受害者缓存条目，所述替换策略被偏置以驱逐具有干净高速缓存行的高速缓存条目，以驱逐具有脏高速缓存行的高速缓存条目。第二操作包括将从高速缓冲存储器的受害者缓存条目驱逐到高速缓冲存储器的受害缓存存储器，并且第三操作包括转换存储器位置地址，以便将后续存储器的地址范围内的存储器位置地址进行混洗和扩展。相信这些操作的各种组合可以提供改进的存储器的操作。本文描述了其它方面。

9. 发明授权

US09268686B2 Background reordering—a preventive wear-out control mechanism with limited overhead 有权
标题翻译：背景重新排序 - 具有有限开销的预防性磨损控制机制
公开(公告)号：US09268686B2
公开(公告)日：2016-02-23
申请号：US13991338
申请日：2011-12-05
申请人： Niklas Linkewitsch
发明人： Niklas Linkewitsch
IPC分类号： G06F13/12 , G06F13/38 , G06F12/02 , G06F3/06
CPC分类号： G06F12/0246 , G06F3/0619 , G06F3/0638 , G06F3/065 , G06F3/0679 , G06F2212/7211
摘要： Embodiments of the present disclosure describe background reordering techniques and configurations to prevent wear-out of an integrated circuit device such as a memory device. In one embodiment, a method includes receiving information about one or more incoming access transactions to a memory device from a processor, determining that a wear-leveling operation is to be performed based on a cumulative number of access transactions to the memory device, the cumulative number of access transactions including the one or more incoming access transactions, and performing the wear-leveling operation by mapping a first physical address of the memory device to a second physical address of the memory device based on a pseudo-random mapping function, and copying information from the first physical address to the second physical address. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了用于防止诸如存储器设备的集成电路设备的磨损的背景重排序技术和配置。在一个实施例中，一种方法包括从处理器接收关于存储器设备的一个或多个传入访问事务的信息，基于对存储器设备的访问事务的累积次数确定要执行损耗均衡操作，累积访问事务的数量，包括一个或多个传入访问事务，以及通过基于伪随机映射函数将存储器件的第一物理地址映射到存储器件的第二物理地址来执行损耗均衡操作，并且复制从第一个物理地址到第二个物理地址的信息。可以描述和/或要求保护其他实施例。

10. 发明授权

US08707142B2 Forward error correction de-mapping techniques 有权
标题翻译：前向纠错解映射技术
公开(公告)号：US08707142B2
公开(公告)日：2014-04-22
申请号：US13365295
申请日：2012-02-03
申请人： Niklas Linkewitsch
发明人： Niklas Linkewitsch
IPC分类号： H03M13/03
CPC分类号： H04L1/005 , H03M13/2909 , H04J3/0605 , H04L1/0041 , H04L1/0057
摘要： Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.
摘要翻译：简而言之，提供不同级别的增强的前向纠错而不修改帧的线速率的技术。

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