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1. 发明授权

US07254678B2 Enhanced STCX design to improve subsequent load efficiency 有权
标题翻译：增强的STCX设计，以提高后续的负载效率
公开(公告)号：US07254678B2
公开(公告)日：2007-08-07
申请号：US11082761
申请日：2005-03-17
申请人： Gregory William Alexander , Juan Jose Arevalo , Balaram Sinharoy , Shih-Hsiung Stephen Tung
发明人： Gregory William Alexander , Juan Jose Arevalo , Balaram Sinharoy , Shih-Hsiung Stephen Tung
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834
摘要： A method, system and computer program product for processing in a multiprocessor data processing system are disclosed. The method includes, in response to executing a load-and-reserve instruction in a processor core, the processing core sending a load-and-reserve operation for an address to a lower level cache of a memory hierarchy, invalidating data for the address in a store-through upper level cache, and placing data returned from the lower level cache into the store-through upper level cache.
摘要翻译：公开了一种用于在多处理器数据处理系统中处理的方法，系统和计算机程序产品。该方法包括响应于在处理器核心中执行加载和保留指令，处理核心向地址的低级缓存发送地址的加载和预留操作，使存储器层次结构中的地址的数据无效通过存储的上级缓存，并将从较低级别高速缓存返回的数据放置到通过存储的上级缓存中。

2. 发明授权

US6112297A Apparatus and method for processing misaligned load instructions in a processor supporting out of order execution 失效
标题翻译：在处理器中处理不对齐负载指令的装置和方法，该处理器支持无序执行
公开(公告)号：US6112297A
公开(公告)日：2000-08-29
申请号：US21133
申请日：1998-02-10
申请人： David Scott Ray , Barry Duane Williamson , Shih-Hsiung Stephen Tung
发明人： David Scott Ray , Barry Duane Williamson , Shih-Hsiung Stephen Tung
IPC分类号： G06F12/08 , G06F9/312 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3816
摘要： One aspect of the invention relates to a method for processing load instructions in a superscalar processor having a data cache and a register file. In one embodiment, the method includes the steps of dispatching a misaligned load instruction to access a block of data that is misaligned in the cache; while continuing to dispatch aligned instructions: generating a first access and a final access to the cache in response to the misaligned load instruction; storing data retrieved from the first access until data from the final access is available; reassembling the data from the first and final access into the order required by the load instruction; and storing the re-assembled data to the register file.
摘要翻译：本发明的一个方面涉及一种用于在具有数据高速缓存和寄存器文件的超标量处理器中处理加载指令的方法。在一个实施例中，该方法包括以下步骤：调度未对准加载指令以访问在高速缓存中未对准的数据块; 同时继续调度对准的指令：响应于未对准的加载指令产生对高速缓存的第一访问和最终访问; 存储从第一访问检索的数据，直到来自最终访问的数据可用; 将来自第一次和最后访问的数据重新组装成加载指令所要求的顺序; 并将重新组装的数据存储到寄存器文件中。

3. 发明授权

US06108753A Cache error retry technique 失效
标题翻译：缓存错误重试技术
公开(公告)号：US06108753A
公开(公告)日：2000-08-22
申请号：US52457
申请日：1998-03-31
申请人： Douglas Craig Bossen , Manratha Rajasekharaiah Jaisimha , Avijit Saha , Shih-Hsiung Stephen Tung
发明人： Douglas Craig Bossen , Manratha Rajasekharaiah Jaisimha , Avijit Saha , Shih-Hsiung Stephen Tung
IPC分类号： G06F11/10 , G06F11/14 , G06F12/08 , G06F9/30
CPC分类号： G06F11/141 , G06F11/1064 , G06F12/0802 , G06F2201/81 , G06F2201/88
摘要： A method and apparatus is provided for enhanced error correction processing through a retry mechanism. When an L1 cache instruction line error is detected, either by a parity error detection process or by an ECC (error correcting code) or other process, the disclosed methodology will schedule an automatic retry of the event that caused the line error without re-booting the entire system. Thereafter, if the error remains present after a predetermined number of retries to load the requested data from L1 cache, then a second level of corrective action is undertaken. The second level corrective action includes accessing an alternate memory location, such as the L2 cache for example. If the state of the requested cache line is exclusive or shared, then an artificial L1 miss is generated for use in enabling an L2 access for the requested cache line. If the requested cache line still does not load from the L2 cache, the second level corrective methodology, after a selective number of retries, terminates and a machine check is generated to initiate a more extensive corrective or recovery action procedure. In an exemplary embodiment, a mechanism is illustrated for recovery from transient errors in an L1 cache load operation although the disclosed methodology may also be implemented partially or entirely in software and in any parity or other error detecting application.
摘要翻译：提供了一种通过重试机制来增强纠错处理的方法和装置。当检测到L1高速缓存指令行错误时，无论是通过奇偶校验错误检测过程还是通过ECC（纠错码）或其他过程，所公开的方法将调度导致线路错误的事件的自动重试，而不需要重新启动整个系统。此后，如果在经过预定次数的重试以从L1高速缓存加载所请求的数据之后仍存在错误，则进行第二级的校正动作。第二级纠正措施包括访问备用存储器位置，例如L2缓存。如果所请求的高速缓存行的状态是独占的或共享的，则生成人造L1小命令用于对所请求的高速缓存行启用L2访问。如果请求的高速缓存行仍然不从L2高速缓存加载，则在选择性重试次数终止之后，第二级校正方法被生成，并且生成机器检查以启动更广泛的纠正或恢复操作过程。在示例性实施例中，示出了用于从L1高速缓存加载操作中的瞬态错误中恢复的机制，尽管所公开的方法也可部分地或完全地以软件和任何奇偶校验或其他错误检测应用程序来实现。

4. 发明授权

US06298417B1 Pipelined cache memory deallocation and storeback 有权
标题翻译：流水线缓存存储器释放和存储
公开(公告)号：US06298417B1
公开(公告)日：2001-10-02
申请号：US09196906
申请日：1998-11-20
申请人： Kin Shing Chan , Dwain Alan Hicks , Michael John Mayfield , Shih-Hsiung Stephen Tung
发明人： Kin Shing Chan , Dwain Alan Hicks , Michael John Mayfield , Shih-Hsiung Stephen Tung
IPC分类号： G06F1200
CPC分类号： G06F12/0859 , G06F12/0804
摘要： A deallocation pipelining circuit for use in a cache memory subsystem. The pipelining circuit is configured to initiate a storeback buffer (SBB) transfer of first line data stored in a first line of a cache memory array if the deallocation pipelining circuit detects a cache miss signal corresponding to the first line and identifies the first line data as modified data. The deallocation pipelining circuit is configured to issue a storeback request signal to a bus interface unit after the completion of the SBB transfer. The circuit initiates a bus interface unit transfer of the first line data after receiving a data acknowledge signal from the bus interface unit. The pipelining circuit is still further configured to deallocate the first line of the cache memory after receiving a request acknowledge signal from the bus interface unit. This deallocation of the first line of the cache memory occurs regardless of a completion status of the bus interface unit transfer whereby a pending fill of the first cache line may proceed prior to completion of the bus interface unit transfer. In one embodiment, the storeback buffer includes first and second segments for storing first and second segment data respectively. In this embodiment, the deallocation pipelining circuit is able to detect the completion of the transfer of the first segment data during the bus interface unit transfer and preferably configured to initiate an SBB transfer of second line data from a second line in the cache memory array in response to the completion of the first segment data transfer. In this manner, the initiation of the second line SBB transfer precedes the completion of the first line bus interface unit transfer.
摘要翻译：用于高速缓存存储器子系统中的一个释放流水线电路。流水线电路被配置为如果分配流水线电路检测到与第一行对应的高速缓存未命中信号并且将第一行数据标识为第一行数据，则启动存储在高速缓冲存储器阵列的第一行中的第一行数据的存储缓冲器（SBB）传送修改数据。配置流水线电路被配置为在SBB传送完成之后向总线接口单元发出存储请求信号。在从总线接口单元接收到数据确认信号之后，该电路启动总线接口单元传送第一行数据。流水线电路还被配置为在从总线接口单元接收到请求确认信号之后解除对高速缓冲存储器的第一行的分配。无论总线接口单元传送的完成状态如何，高速缓冲存储器的第一行的解除分配都会发生，从而可以在完成总线接口单元传输之前继续执行第一高速缓存行的填充。在一个实施例中，存储缓冲器包括用于分别存储第一和第二段数据的第一和第二段。在该实施例中，解除分配流水线电路能够在总线接口单元传送期间检测到第一段数据的传送完成，并且优选地被配置为发起来自高速缓存存储器阵列中的第二行的第二行数据的SBB传送响应完成第一段数据传输。以这种方式，第二线路SBB传送的启动先于第一线路总线接口单元传送的完成。

5. 发明授权

US6085291A System and method for selectively controlling fetching and prefetching of data to a processor 失效
标题翻译：用于选择性地控制将数据提取和预取到处理器的系统和方法
公开(公告)号：US6085291A
公开(公告)日：2000-07-04
申请号：US554180
申请日：1995-11-06
申请人： Dwain Alan Hicks , Michael John Mayfield , David Scott Ray , Shih-Hsiung Stephen Tung
发明人： Dwain Alan Hicks , Michael John Mayfield , David Scott Ray , Shih-Hsiung Stephen Tung
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/383 , G06F12/0862 , G06F2212/6022 , G06F2212/6026
摘要： Within a data processing system implementing primary and secondary caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. Prefetching may be performed on cache misses or hits. Cache misses on successive cache lines may allocate a stream of cache lines to the stream buffers. Control circuitry, coupled to a stream filter circuit, selectively controls fetching and prefetching of data from system memory to the primary and secondary caches associated with a processor and to a stream buffer circuit.
摘要翻译：在实现主和次高速缓存和流过滤器和缓冲器的数据处理系统中，缓存行的预取以渐进的方式执行。在一种模式下，数据可能不被预取。在第二模式中，预取两条高速缓存线，其中一行被预取到L1高速缓存中，并且下一行被预取到流缓冲器中。在第三种模式下，一次预取多于两条的高速缓存行。可以在高速缓存未命中或命中时执行预取。连续缓存行上的缓存未命中可能会将流缓存行分配给流缓冲区。耦合到流滤波器电路的控制电路选择性地控制数据从系统存储器到与处理器和流缓冲器电路相关联的主和次高速缓存的取样和预取。

6. 发明授权

US06463514B1 Method to arbitrate for a cache block 失效
标题翻译：仲裁缓存块的方法
公开(公告)号：US06463514B1
公开(公告)日：2002-10-08
申请号：US09025605
申请日：1998-02-18
申请人： David Scott Ray , Shih-Hsiung Stephen Tung , Pei Chun Liu
发明人： David Scott Ray , Shih-Hsiung Stephen Tung , Pei Chun Liu
IPC分类号： G06F1200
CPC分类号： G06F12/0851 , G06F12/0857
摘要： A method of arbitrating between cache access circuits (i.e., load/store units) by stalling a first cache access circuit in response to detection of a conflict between a first cache address and a second cache address. The stalling is performed in response to a comparison of one or more subarray selection bits in each of the first and second cache addresses, and further preferably includes a common contention logic unit for both the first and second cache access circuits. The first cache address is retained within the first cache access circuit so that the first cache access circuit does not need to re-generate the first cache address. If the same word (or doubleword) is being accessed by multiple load operations, this condition is not considered contention and both operations are allowed to proceed, even though they are in the same subarray of the interleaved cache.
摘要翻译：响应于检测到第一高速缓存地址和第二高速缓存地址之间的冲突而通过停止第一高速缓存访问电路来在高速缓存访问电路之间进行仲裁（即，加载/存储单元）的方法。响应于第一和第二高速缓存地址中的每一个中的一个或多个子阵列选择位的比较来执行停滞，并且还优选地包括用于第一和第二高速缓存存取电路的公共竞争逻辑单元。第一高速缓存地址被保留在第一高速缓存访问电路内，使得第一高速缓存访问电路不需要重新生成第一高速缓存地址。如果通过多个加载操作访问相同的字（或双字），则该条件不被认为是争用，并且两个操作都被允许继续进行，即使它们在交错高速缓存的相同子阵列中。

7. 发明授权

US06430680B1 Processor and method of prefetching data based upon a detected stride 失效
标题翻译：基于检测到的步幅预取数据的处理器和方法
公开(公告)号：US06430680B1
公开(公告)日：2002-08-06
申请号：US09052567
申请日：1998-03-31
申请人： William Elton Burky , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
发明人： William Elton Burky , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
IPC分类号： G06F900
CPC分类号： G06F9/3455 , G06F9/3832
摘要： A processor and method of fetching data within a data processing system are disclosed. According to the method, a first difference between a first load address and a second load address is calculated. In addition, a determination is made whether a second difference between a third load address and the second load address is equal to the first difference. In response to a determination that the first difference and the second difference are equal, a fourth load address, which is generated by adding the third address and the second difference, is transmitted to the memory as a memory fetch address. In an embodiment of the data processing system including a processor having an associated cache, the fourth load address is transmitted to the memory only if the fourth load address is not resident in the cache or the target of an outstanding memory fetch request.
摘要翻译：公开了一种在数据处理系统内取出数据的处理器和方法。根据该方法，计算第一加载地址和第二加载地址之间的第一差。此外，确定第三加载地址和第二加载地址之间的第二差是否等于第一差。响应于确定第一差异和第二差异相等，通过将第三地址和第二差值相加产生的第四加载地址作为存储器提取地址被发送到存储器。在包括具有关联高速缓存的处理器的数据处理系统的实施例中，仅当第四加载地址不驻留在高速缓存中或未完成的存储器提取请求的目标时才将第四加载地址发送到存储器。

8. 发明授权

US06240487B1 Integrated cache buffers 失效
标题翻译：集成缓存缓存
公开(公告)号：US06240487B1
公开(公告)日：2001-05-29
申请号：US09025606
申请日：1998-02-18
申请人： Pei-Chun Peter Liu , Rajinder Paul Singh , Shih-Hsiung Stephen Tung , Dwain Alan Hicks , Kin Shing Chan
发明人： Pei-Chun Peter Liu , Rajinder Paul Singh , Shih-Hsiung Stephen Tung , Dwain Alan Hicks , Kin Shing Chan
IPC分类号： G06F1208
CPC分类号： G06F12/0859 , G06F12/0851
摘要： A cache has an array for holding data or instruction values, a buffer connected to the array, and means for accessing the buffer to retrieve a value for a processing unit. The accessing means uses wires having a pitch which is substantially equal to a wire pitch of the cache array. Multiplexers can be used with a plurality of such buffers to create a common output path. The cache can be interleaved, with the array being a first subarray, and the buffer being a first buffer, and further comprising a second subarray and a second buffer, wherein the first and second buffers separate the first and second subarrays. The invention can be applied to a store-back buffer as well as a reload buffer.
摘要翻译：高速缓存具有用于保存数据或指令值的阵列，连接到该阵列的缓冲器，以及用于访问缓冲器以检索处理单元的值的装置。访问装置使用具有基本上等于高速缓存阵列的线间距的间距的线。多路复用器可以与多个这样的缓冲器一起使用以创建公共输出路径。高速缓存可以被交织，阵列是第一子阵列，缓冲器是第一缓冲器，并且还包括第二子阵列和第二缓冲器，其中第一和第二缓冲器分离第一和第二子阵列。本发明可以应用于存储缓冲器以及重新加载缓冲器。

9. 发明授权

US06446170B1 Efficient store machine in cache based microprocessor 失效
标题翻译：高效存储机器在基于缓存的微处理器中
公开(公告)号：US06446170B1
公开(公告)日：2002-09-03
申请号：US09232239
申请日：1999-01-19
申请人： Kin Shing Chan , Dwain Alan Hicks , Michael John Mayfield , Shih-Hsiung Stephen Tung
发明人： Kin Shing Chan , Dwain Alan Hicks , Michael John Mayfield , Shih-Hsiung Stephen Tung
IPC分类号： G06F1200
CPC分类号： G06F9/3824
摘要： A method of retiring operations to a cache. Initially, a first operation is queued in a stack such as the store queue of a retire unit. The first operation is then copied, in a first transfer, to a latch referred to as the miss latch in response to a resource conflict that prevents the first operation from accessing the cache. The first operation is maintained in the stack for the duration of the resource conflict. When the resource conflict is resolved, the cache is accessed, in a first cache access, with the first operation from the stack. Preferably, the first operation is removed from the stack when the resource conflict is resolved and the first cache access is initiated. In the preferred embodiment, the first operation is maintained in the miss latch until the first cache access results in a cache hit. One embodiment of the invention further includes accessing the cache, in a first miss access, with the first operation from the miss latch in response to a cache miss that resulted from the first cache access. In a presently preferred embodiment, a second access is executed to access the cache with a second operation queued in the stack in response to a cache hit resulting from the first cache access. The first and second cache accesses preferably occur in consecutive cycles. Typically, the first and second operations are store operations that are queued in the stack in program order. In one embodiment the first operation is removed from the stack upon resolving of the resource conflict.
摘要翻译：一种退出到缓存的操作的方法。最初，第一操作在诸如退出单元的存储队列的堆栈中排队。然后，响应于防止第一操作访问高速缓存的资源冲突，第一操作在第一传送中被复制到被称为未命中锁存器的锁存器。在资源冲突的持续时间内，第一个操作被保留在堆栈中。当解决资源冲突时，在第一个高速缓存访问中，缓存从堆栈中进行第一个操作。优选地，当解决资源冲突并启动第一高速缓存访问时，第一操作从堆栈中移除。在优选实施例中，第一操作保持在未命中锁存器中，直到第一高速缓存访问导致高速缓存命中。本发明的一个实施例还包括响应于由第一高速缓存访问引起的高速缓存未命中，以第一未命中访问的速度访问来自未命中锁存器的第一操作。在当前优选的实施例中，响应于由第一高速缓存访问导致的高速缓存命中，执行第二访问以访问在堆栈中排队的第二操作的高速缓存。第一和第二高速缓存访问优选地在连续的周期中进行。通常，第一和第二操作是以程序顺序排列在堆栈中的存储操作。在一个实施例中，在解决资源冲突时，第一操作从堆栈中移除。

10. 发明授权

US06275918B1 Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold 失效
标题翻译：从增加访问指示符阈值的数量获取历史表信息中的载入目标操作数预取地址
公开(公告)号：US06275918B1
公开(公告)日：2001-08-14
申请号：US09268307
申请日：1999-03-16
申请人： William Elton Burky , Peter Steven Lenk , Dung Quoc Nguyen , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
发明人： William Elton Burky , Peter Steven Lenk , Dung Quoc Nguyen , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
IPC分类号： G06F934
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832
摘要： A method and system for improving pre-fetch accuracy in a data processing system utilizing a pre-fetch history table is disclosed. The method compares a portion of an instruction address to an address located as an entry in a pre-fetch history table based on the status of a validity bit contained in the entry. If the validity bit is set and the addresses match, an indicator field within the entry is checked to see if it is equal to or greater than a threshold level. When the indicator field is greater than the threshold level, a target operand address is pre-fetched based on stride and direction.
摘要翻译：公开了一种利用预取历史表改善数据处理系统中的预取精度的方法和系统。该方法基于条目中包含的有效位的状态，将指令地址的一部分与位于预取历史表中的条目的地址进行比较。如果有效位被设置并且地址匹配，则检查条目内的指示符字段以查看其是否等于或大于阈值级别。当指示符字段大于阈值电平时，将根据步幅和方向预取目标操作数地址。

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