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1. 发明授权

US07254678B2 Enhanced STCX design to improve subsequent load efficiency 有权
标题翻译：增强的STCX设计，以提高后续的负载效率
公开(公告)号：US07254678B2
公开(公告)日：2007-08-07
申请号：US11082761
申请日：2005-03-17
申请人： Gregory William Alexander , Juan Jose Arevalo , Balaram Sinharoy , Shih-Hsiung Stephen Tung
发明人： Gregory William Alexander , Juan Jose Arevalo , Balaram Sinharoy , Shih-Hsiung Stephen Tung
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834
摘要： A method, system and computer program product for processing in a multiprocessor data processing system are disclosed. The method includes, in response to executing a load-and-reserve instruction in a processor core, the processing core sending a load-and-reserve operation for an address to a lower level cache of a memory hierarchy, invalidating data for the address in a store-through upper level cache, and placing data returned from the lower level cache into the store-through upper level cache.
摘要翻译：公开了一种用于在多处理器数据处理系统中处理的方法，系统和计算机程序产品。该方法包括响应于在处理器核心中执行加载和保留指令，处理核心向地址的低级缓存发送地址的加载和预留操作，使存储器层次结构中的地址的数据无效通过存储的上级缓存，并将从较低级别高速缓存返回的数据放置到通过存储的上级缓存中。

2. 发明授权

US07120784B2 Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment 失效
标题翻译：通过在同时多线程处理环境中逻辑分割分支历史表和预测目标地址缓存来进行线程专用分支预测
公开(公告)号：US07120784B2
公开(公告)日：2006-10-10
申请号：US10425064
申请日：2003-04-28
申请人： Gregory William Alexander , Scott Bruce Frommer , David Stephen Levitan , Balaram Sinharoy
发明人： Gregory William Alexander , Scott Bruce Frommer , David Stephen Levitan , Balaram Sinharoy
IPC分类号： G06F9/40 , G06F9/00
CPC分类号： G06F9/3806 , G06F9/30189 , G06F9/3844 , G06F9/3851
摘要： Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and predicted target address cache would provide better results for branch prediction. The branch prediction logic responds to the occurrence of the monitored condition by logically splitting the BHTs and count cache so that half of the address space is allocated to a first thread and the second half is allocated to the next thread. Prediction-generated addresses that belong to the first thread are then directed to the half of the array that is allocated to that thread and prediction-generated addresses that belong to the second thread are directed to the next half of the array that is allocated to the second thread. In order to split the array, the highest order bit in the array is utilized to uniquely identify addresses of the first and the second threads.
摘要翻译：分支预测逻辑被增强以提供用于某些条件的监视功能，其指示使用单独的BHT和预测的目标地址高速缓存将为分支预测提供更好的结果。分支预测逻辑通过逻辑分割BHT和计数高速缓存来响应监视条件的发生，使得一半的地址空间被分配给第一个线程，而后半部分被分配给下一个线程。属于第一个线程的预测生成的地址然后被定向到分配给该线程的数组的一半，并且属于第二个线程的预测生成的地址被定向到分配给该线程的数组的下一半第二线程。为了拆分阵列，阵列中的最高位用于唯一标识第一和第二个线程的地址。

3. 发明授权

US07039768B2 Cache predictor for simultaneous multi-threaded processor system supporting multiple transactions 有权
标题翻译：支持多个事务的同时多线程处理器系统的缓存预测器
公开(公告)号：US07039768B2
公开(公告)日：2006-05-02
申请号：US10424487
申请日：2003-04-25
申请人： Gregory William Alexander , David Stephen Levitan , Balaram Sinharoy
发明人： Gregory William Alexander , David Stephen Levitan , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/1054 , G06F2212/6082
摘要： A set-associative I-cache that enables early cache hit prediction and correct way selection when the processor is executing instructions of multiple threads having similar EAs. Each way of the I-cache comprises an EA Directory (EA Dir), which includes a series of thread valid bits that are individually assigned to one of the multiple threads. Particular ones of the thread valid bits are set in each EA Dir to indicate when an instruction block the thread is cached within the particular way with which the EA Dir is associated. When a cache line request for a particular thread is received, a cache hit is predicted when the EA of the request matches the EA in the EA Dir and the cache line is selected from the way associated with the EA Dir who has the thread valid bit for that thread set. Early way selection is thus achieved since the way selection only requires a check of the thread valid bits.
摘要翻译：当处理器执行具有类似EA的多个线程的指令时，能够实现早期缓存命中预测和正确选择方法的集合关联I缓存。 I缓存的每个方式包括EA目录（EA目录），其包括单独分配给多个线程之一的一系列线程有效位。在每个EA Dir中设置特定的线程有效位，以指示线程是否以EA Dir所关联的特定方式缓存的时间。当接收到针对特定线程的高速缓存线请求时，当请求的EA与EA Dir中的EA匹配时，预测缓存命中，并且从与具有线程有效位的EA Dir相关联的方式中选择高速缓存行为该线程集。因此，由于选择方式仅需要检查线程有效位，因此实现了早期方式选择。

4. 发明授权

US08707016B2 Thread partitioning in a multi-core environment 有权
标题翻译：多核环境中的线程分区
公开(公告)号：US08707016B2
公开(公告)日：2014-04-22
申请号：US12024211
申请日：2008-02-01
申请人： Ravi K. Arimilli , Juan C. Rubio , Balaram Sinharoy
发明人： Ravi K. Arimilli , Juan C. Rubio , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. The set of helper thread binaries and the set of main thread binaries are partitioned according to common instruction boundaries. As a first partition in the set of main thread binaries executes within a first core, a second partition in the set of helper thread binaries executes within a second core, thus “warming up” the cache in the second core. When the first partition of the main completes execution, a second partition of the main core moves to the second core, and executes using the warmed up cache in the second core.
摘要翻译：创建一组辅助线程二进制文件来检索一组主线程二进制文件使用的数据。辅助线程二进制文件集和主线程二进制文件集合根据公共指令边界进行分区。作为主线程二进制文件集合中的第一分区在第一核心内执行，该辅助线程二进制文件集中的第二分区在第二核心内执行，从而“预热”第二核心中的高速缓存。当主要的第一分区完成执行时，主核心的第二分区移动到第二核心，并使用第二核心中的预热高速缓存执行。

5. 发明授权

US08612730B2 Hardware assist thread for dynamic performance profiling 失效
标题翻译：用于动态性能分析的硬件辅助线
公开(公告)号：US08612730B2
公开(公告)日：2013-12-17
申请号：US12796124
申请日：2010-06-08
申请人： Ronald P. Hall , Venkat Rajeev Indukuru , Alexander Erik Mericas , Balaram Sinharoy , Zhong Liang Wang
发明人： Ronald P. Hall , Venkat Rajeev Indukuru , Alexander Erik Mericas , Balaram Sinharoy , Zhong Liang Wang
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/327 , G06F11/3466 , G06F2201/865 , G06F2201/88
摘要： A method and data processing system for managing running of instructions in a program. A processor of the data processing system receives a monitoring instruction of a monitoring unit. The processor determines if at least one secondary thread of a set of secondary threads is available for use as an assist thread. The processor selects the at least one secondary thread from the set of secondary threads to become the assist thread in response to a determination that the at least one secondary thread of the set of secondary threads is available for use as an assist thread. The processor changes profiling of running of instructions in the program from the main thread to the assist thread.
摘要翻译：一种用于管理程序中的指令的运行的方法和数据处理系统。数据处理系统的处理器接收监视单元的监视指令。处理器确定一组辅助线程的至少一个辅助线程是否可用作辅助线程。响应于确定所述一组次要线程的至少一个辅助线程可用作辅助线程，所述处理器从所述辅助线程组中选择所述至少一个辅助线程以成为所述辅助线程。处理器将程序中指令的运行情况从主线程更改为辅助线程。

6. 发明授权

US08387065B2 Speculative popcount data creation 有权
标题翻译：投机性的popcount数据创建
公开(公告)号：US08387065B2
公开(公告)日：2013-02-26
申请号：US12425343
申请日：2009-04-16
申请人： Ravi K. Arimilli , Ronald N. Kalla , Balaram Sinharoy
发明人： Ravi K. Arimilli , Ronald N. Kalla , Balaram Sinharoy
IPC分类号： G06F9/46 , G06F9/45 , G06F9/30 , G06F9/40
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/3842
摘要： A method and a data processing system by which population count (popcount) operations are efficiently performed without incurring the latency and loss of critical processing cycles and bandwidth of real time processing. The method comprises: identifying data to be stored to memory for which a popcount may need to be determined; speculatively performing a popcount operation on the data as a background process of the processor while the data is being stored to memory; storing the data to a first memory location; and storing a value of the popcount generated by the popcount operation within a second memory location. The method further comprises: determining a size of data; determining a granular level at which the popcount operation on the data will be performed; and reserving a size of said second memory location that is sufficiently large to hold the value of the popcount.
摘要翻译：一种方法和数据处理系统，通过该方法和数据处理系统有效地执行人口计数（popcount）操作，而不会导致关键处理周期的延迟和丢失以及实时处理的带宽。该方法包括：识别要存储到可能需要确定一个弹出窗口的存储器的数据; 在将数据存储到存储器中的情况下，作为处理器的后台处理推测性地对数据进行弹出数据操作; 将数据存储到第一存储器位置; 以及将由所述popcount操作生成的所述popcount的值存储在第二存储器位置内。该方法还包括：确定数据的大小; 确定将执行对数据的弹出数据操作的粒度级别; 以及保留所述第二存储器位置的大小足够大以保持所述用户名的值。

7. 发明授权

US08359589B2 Helper thread for pre-fetching data 失效
标题翻译：辅助线程用于预取数据
公开(公告)号：US08359589B2
公开(公告)日：2013-01-22
申请号：US12024191
申请日：2008-02-01
申请人： Ravi K. Arimilli , Juan C. Rubio , Balaram Sinharoy
发明人： Ravi K. Arimilli , Juan C. Rubio , Balaram Sinharoy
IPC分类号： G06F9/44 , G06F9/45 , G06F15/167 , G06F9/30 , G06F9/46
CPC分类号： G06F8/41 , G06F9/383 , G06F9/3851
摘要： A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. If executing a portion of the set of helper thread binaries results in the retrieval of data needed by the set of main thread binaries, then that retrieved data is utilized by the set of main thread binaries.
摘要翻译：创建一组辅助线程二进制文件来检索一组主线程二进制文件使用的数据。如果执行一组辅助线程二进制文件的一部分导致检索主线程二进制文件集所需的数据，那么该检索的数据由主线程二进制文件集合使用。

8. 发明授权

US08285971B2 Block driven computation with an address generation accelerator 失效
标题翻译：使用地址生成加速器进行块驱动计算
公开(公告)号：US08285971B2
公开(公告)日：2012-10-09
申请号：US12336315
申请日：2008-12-16
申请人： Ravi K. Arimilli , Balaram Sinharoy
发明人： Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/30094 , G06F9/345
摘要： A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, an instruction sequencing unit that fetches instructions for execution by the at least one execution unit, and an address generation accelerator. The address generation accelerator, responsive to an initiation signal received from the instruction sequencing unit, computes and outputs first and second effective addresses of operands of an operation.
摘要翻译：处理器包括执行指令的至少一个执行单元，耦合到所述至少一个执行单元的至少一个寄存器文件，其缓冲由所述至少一个执行单元访问的操作数，指令排序单元，其通过所述至少一个执行单元和地址生成加速器。地址产生加速器响应于从指令排序单元接收的发起信号，计算并输出操作的操作数的第一和第二有效地址。

9. 发明授权

US08266381B2 Varying an amount of data retrieved from memory based upon an instruction hint 失效
标题翻译：根据指令提示改变从存储器检索的数据量
公开(公告)号：US08266381B2
公开(公告)日：2012-09-11
申请号：US12024170
申请日：2008-02-01
申请人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0822 , G06F2212/507 , G06F2212/6028
摘要： In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the load instruction is not associated with a hint, the processor retrieves a full cache line of data from the memory hierarchy into the processor in response to the load instruction. In response to detecting that the load instruction is associated with a hint, a processor retrieves a partial cache line of data into the processor from the memory hierarchy in response to the load instruction.
摘要翻译：在至少一个实施例中，处理器在执行程序代码期间检测程序代码内的加载指令是否与提示相关联。响应于检测到加载指令不与提示相关联，处理器响应于加载指令从存储器层次结构检索完整的高速缓存行数据到处理器。响应于检测到加载指令与提示相关联，处理器响应于加载指令从存储器层次结构检索数据的部分高速缓存行到处理器中。

10. 发明授权

US08140764B2 System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory 有权
标题翻译：用于重新配置具有与下级高速缓冲存储器的扇区相关联的访问位的高速缓冲存储器的系统和与上级高速缓冲存储器的扇区相关联的粒度位
公开(公告)号：US08140764B2
公开(公告)日：2012-03-20
申请号：US12985726
申请日：2011-01-06
申请人： Xiaowei Shen , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
发明人： Xiaowei Shen , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.
摘要翻译：提供了一种重新配置高速缓冲存储器的方法。一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征，并且基于所分析的一个或多个特征重新配置高速缓存。分析特性的示例可以包括但不限于执行实体使用的数据结构，执行实体的预期参考模式，执行实体的类型，执行实体的热和功耗。等等重新配置可以包括但不限于高速缓冲存储器的相关性，可用于存储数据的高速缓冲存储器的量，高速缓冲存储器的相干粒度，高速缓存存储器的行大小等。

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