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1. 发明授权

US08117367B2 Processor system with an application and a maintenance function 有权
标题翻译：具有应用和维护功能的处理器系统
公开(公告)号：US08117367B2
公开(公告)日：2012-02-14
申请号：US13028459
申请日：2011-02-16
申请人： Gregory R. Conti , Franck Dahan
发明人： Gregory R. Conti , Franck Dahan
IPC分类号： G06F13/24 , G06F9/46
CPC分类号： G06F13/24 , Y02D10/14
摘要： A processor system with an application and a maintenance function that would interfere with the application if concurrently executed. The processor system comprises a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output. The processor system also comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application.
摘要翻译：具有应用程序和维护功能的处理器系统，如果同时执行则会干扰应用程序。处理器系统包括可在不同安全性和上下文相关模式下操作的一组处理器核心，所述处理器具有至少一个中断输入和至少一个等待中断输出。所述处理器系统还包括响应于所述至少一个等待中断输出以提供中断信号的等待中断扩展电路，所述处理器核中的至少一个可响应于所述中断信号而可操作以调度在时间上分离的维护功能执行应用程序。

2. 发明授权

US08069290B2 Processing system operable in various execution environments 有权
标题翻译：可在各种执行环境中操作的处理系统
公开(公告)号：US08069290B2
公开(公告)日：2011-11-29
申请号：US13028416
申请日：2011-02-16
申请人： Gregory R. Conti , Franck Dahan
发明人： Gregory R. Conti , Franck Dahan
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs. The system also comprises a register coupled to at least one of the processor cores for identifying active execution environments. The system also comprises a global interrupt handler operable to selectively route interrupts to one or more of the interrupt inputs of said plural processor cores. The system also comprises a conversion circuit having plural interrupt-related output lines, and said conversion circuit fed with at least some of said respective wait for interrupt outputs and respective security outputs and fed by said register.
摘要翻译：可在各种执行环境中操作的处理系统。该系统包括具有各自的中断输入的多个处理器核，各自等待中断输出和相应的安全输出。该系统还包括耦合到至少一个处理器核心的寄存器，用于识别主动执行环境。该系统还包括全局中断处理器，其可操作以选择性地将中断路由到所述多个处理器核的一个或多个中断输入。该系统还包括具有多个中断相关输出线的转换电路，并且所述转换电路馈送至少一些所述相应的等待中断输出和相应的安全输出并由所述寄存器馈送。

3. 发明授权

US08055828B2 Electronic power management system 有权
标题翻译：电子电源管理系统
公开(公告)号：US08055828B2
公开(公告)日：2011-11-08
申请号：US13028440
申请日：2011-02-16
申请人： Gregory R. Conti , Franck Dahan
发明人： Gregory R. Conti , Franck Dahan
IPC分类号： G06F13/24 , G06F1/26
CPC分类号： G06F13/24 , Y02D10/14
摘要： An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for interrupt output. The system further comprises a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs. The system further comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processors operable to configure said power control circuit in response to the interrupt signal.
摘要翻译：一种电子电源管理系统，包括可在不同安全性和上下文相关模式下操作的多个处理器，并且具有相应的电源电压输入和时钟输入，所述处理器具有至少一个中断输入和至少一个等待中断输出。该系统还包括功率控制电路，其可操作以可配置地调节所述电源电压输入和时钟输入的电源电压和时钟速率。所述系统还包括响应于所述至少一个等待中断输出以提供中断信号的等待中断扩展电路，所述处理器中的至少一个可操作以响应于所述中断信号配置所述功率控制电路。

4. 发明授权

US08812804B2 Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices 有权
标题翻译：用于处理器设备的安全需求寻呼和其他寻呼操作的方法，装置和系统
公开(公告)号：US08812804B2
公开(公告)日：2014-08-19
申请号：US13345484
申请日：2012-01-06
申请人： Steven C. Goss , Gregory R. Conti , Narendar Shankar , Mehdi-Laurent Akkar , Aymeric Vial
发明人： Steven C. Goss , Gregory R. Conti , Narendar Shankar , Mehdi-Laurent Akkar , Aymeric Vial
IPC分类号： G06F12/14 , G06F12/12 , G06F12/00 , G06F12/02 , H04B1/38 , H04L29/06 , H04W12/06 , G06F21/57 , G06F21/79
CPC分类号： H04L9/3236 , G06F9/45558 , G06F9/461 , G06F12/0246 , G06F12/08 , G06F12/1408 , G06F12/145 , G06F12/1483 , G06F21/575 , G06F21/79 , G06F2009/45583 , G06F2009/45587 , G06F2212/171 , G06F2212/402 , G06F2212/7201 , H04L9/0897 , H04L63/123 , H04L63/18 , H04L63/20 , H04W12/06 , H04W12/10
摘要： A secure demand paging (SDP) system includes a dynamic random access memory (DRAM), a microprocessor having a secure internal memory and coupled to said DRAM, and a non-volatile memory storing a representation of operations accessible by the microprocessor. The stored representation of operations includes a coded physical representation of operations to configure an SDP space in the DRAM, to organize the SDP space into virtual machine contexts, to organize at least one of the virtual machine contexts into block book keeping blocks and book keeping spaces in the block book keeping blocks, and to execute a secure demand paging process between said secure internal memory and said DRAM.
摘要翻译：安全需求寻呼（SDP）系统包括动态随机存取存储器（DRAM），具有安全内部存储器并耦合到所述DRAM的微处理器以及存储由微处理器访问的操作表示的非易失性存储器。存储的操作表示包括用于配置DRAM中的SDP空间的操作的编码物理表示，以将SDP空间组织成虚拟机上下文，以将虚拟机上下文中的至少一个组织成块保存块和保存空间并且在所述安全内部存储器和所述DRAM之间执行安全需求寻呼处理。

5. 发明授权

US07809934B2 Security measures for preventing attacks that use test mechanisms 有权
标题翻译：防止使用测试机制的攻击的安全措施
公开(公告)号：US07809934B2
公开(公告)日：2010-10-05
申请号：US11741181
申请日：2007-04-27
申请人： Gregory R. Conti , Pascal Cussonneau , Benoit Drevet , Vincent Chalendard
发明人： Gregory R. Conti , Pascal Cussonneau , Benoit Drevet , Vincent Chalendard
IPC分类号： G06F9/00 , G06F12/14
CPC分类号： G06F21/575 , G06F21/74 , G06F2221/2143
摘要： A system comprising processing logic adapted to determine a type of boot performed by the system and a storage coupled to the processing logic. The processing logic is configured to erase or invalidate a predetermined portion of the storage, and to activate or deactivate an interface by which the system is accessed, if the type of boot comprises a functional boot.
摘要翻译：一种系统，包括适于确定由系统执行的引导类型的处理逻辑和耦合到处理逻辑的存储。处理逻辑被配置为擦除或者使存储器的预定部分无效，并且如果引导类型包括功能引导，则激活或停用系统被访问的接口。

6. 发明授权

US08959339B2 Method and system for preventing unauthorized processor mode switches 有权
标题翻译：防止未经授权的处理器模式切换的方法和系统
公开(公告)号：US08959339B2
公开(公告)日：2015-02-17
申请号：US11343061
申请日：2006-01-30
申请人： Gregory R. Conti
发明人： Gregory R. Conti
IPC分类号： G06F21/00 , G06F21/56 , G06F21/52 , G06F21/53 , G06F21/74 , G06F21/81 , H04L29/06
CPC分类号： G06F21/74 , G06F1/24 , G06F1/3287 , G06F21/52 , G06F21/53 , G06F21/567 , G06F21/81 , G06F2221/034 , G06F2221/2101 , G06F2221/2105 , G06F2221/2111 , G06F2221/2113 , G06F2221/2115 , G06F2221/2119 , G06F2221/2141 , G06F2221/2149 , G06F2221/2153 , H04L63/105 , H04L2463/102
摘要： A system comprising a processor adapted to activate multiple security levels for the system and a monitoring device coupled to the processor and employing security rules pertaining to the multiple security levels. The monitoring device restricts usage of the system if the processor activates the security levels in a sequence contrary to the security rules.
摘要翻译：一种系统，包括适于激活所述系统的多个安全级别的处理器和耦合到所述处理器的监视设备并且采用与所述多个安全级别有关的安全规则。如果处理器以与安全规则相反的顺序激活安全级别，则监视设备限制系统的使用。

7. 发明授权

US08108641B2 Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices 有权
标题翻译：用于处理器设备的安全需求寻呼和其他寻呼操作的方法，装置和系统
公开(公告)号：US08108641B2
公开(公告)日：2012-01-31
申请号：US11426597
申请日：2006-06-27
申请人： Steven C. Goss , Gregory R. Conti , Narendar Shankar , Mehdi-Laurent Akkar , Aymeric Vial
发明人： Steven C. Goss , Gregory R. Conti , Narendar Shankar , Mehdi-Laurent Akkar , Aymeric Vial
IPC分类号： G06F12/14
CPC分类号： H04L9/3236 , G06F9/45558 , G06F9/461 , G06F12/0246 , G06F12/08 , G06F12/1408 , G06F12/145 , G06F12/1483 , G06F21/575 , G06F21/79 , G06F2009/45583 , G06F2009/45587 , G06F2212/171 , G06F2212/402 , G06F2212/7201 , H04L9/0897 , H04L63/123 , H04L63/18 , H04L63/20 , H04W12/06 , H04W12/10
摘要： A secure demand paging system (1020) includes a processor (1030) operable for executing instructions, an internal memory (1034) for a first page in a first virtual machine context, an external memory (1024) for a second page in a second virtual machine context, and a security circuit (1038) coupled to the processor (1030) and to the internal memory (1034) for maintaining the first page secure in the internal memory (1034). The processor (1030) is operable to execute sets of instructions representing: a central controller (4210), an abort handler (4260) coupled to supply to the central controller (4210) at least one signal representing a page fault by an instruction in the processor (1030), a scavenger (4220) responsive to the central controller (4210) and operable to identify the first page as a page to free, a virtual machine context switcher (4230) responsive to the central controller (4210) to change from the first virtual machine context to the second virtual machine context; and a swapper manager (4240) operable to swap in the second page from the external memory (1024) with decryption and integrity check, to the internal memory (1034) in place of the first page.
摘要翻译：安全需求寻呼系统（1020）包括可操作以执行指令的处理器（1030），用于第一虚拟机上下文中的第一页的内部存储器（1034），用于第二虚拟机中第二页的外部存储器（1024）机器上下文和耦合到处理器（1030）和内部存储器（1034）的安全电路（1038），用于将第一页面保持在内部存储器（1034）中。处理器（1030）可操作以执行指令集，其表示：中央控制器（4210），中止处理器（4260），其耦合以向所述中央控制器（4210）提供表示页错误的至少一个信号处理器（1030），响应于中央控制器（4210）的清理器（4220），并且可操作以将第一页面识别为页面以释放;响应于中央控制器（4210）的虚拟机上下文切换器（4230）从第一个虚拟机上下文到第二个虚拟机上下文; 以及交换管理器（4240），其可操作以代替所述第一页，将来自所述外部存储器（1024）的解密和完整性检查的第二页面交换到所述内部存储器（1034）。

8. 发明申请

US20080163359A1 Static And Dynamic Firewalls 有权
标题翻译：静态和动态防火墙
公开(公告)号：US20080163359A1
公开(公告)日：2008-07-03
申请号：US11678219
申请日：2007-02-23
申请人： Gregory R. Conti
发明人： Gregory R. Conti
IPC分类号： G06F21/00
CPC分类号： G06F21/79 , G06F12/1441 , G06F12/1491 , G06F21/52 , G06F21/554 , G06F21/71 , G06F21/74
摘要： A system comprising control logic adapted to activate multiple security levels for the system. The system further comprises a storage coupled to the control logic and comprising a stack, the stack associated with one, but not all, of the multiple security levels. The system also comprises security logic coupled to the control logic and adapted to restrict usage of the system if the control logic attempts to fetch an instruction op-code from the stack.
摘要翻译：一种包括适于激活所述系统的多个安全级别的控制逻辑的系统。该系统还包括耦合到控制逻辑并包括堆栈的存储器，该堆栈与多个安全级别中的一个但不是全部相关联。该系统还包括耦合到控制逻辑的安全逻辑，并且如果控制逻辑试图从堆栈获取指令操作码，则适用于限制系统的使用。

9. 发明申请

US20080086769A1 MONITOR MODE INTEGRITY VERIFICATION 审中-公开
标题翻译：监控模式完整性验证
公开(公告)号：US20080086769A1
公开(公告)日：2008-04-10
申请号：US11617411
申请日：2006-12-28
申请人： Gregory R. Conti
发明人： Gregory R. Conti
IPC分类号： G06F17/00
CPC分类号： G06F12/1491 , G06F12/1441 , G06F21/74
摘要： A system comprising a processing logic adapted to activate multiple security levels for the system and a storage coupled to the processing logic via a bus, the bus adapted to transfer information between the storage and the processing logic. The system also comprises a monitoring logic coupled to the processing logic and comprising a range of addresses associated with a predetermined security level of the system. The monitoring logic obtains an address associated with the information. If a current security level matches the predetermined security level and if the address does not correspond to the range of addresses, the monitoring logic restricts usage of the system.
摘要翻译：一种系统，包括适于激活系统的多个安全级别的处理逻辑和经由总线耦合到处理逻辑的存储器，该总线适于在存储器和处理逻辑之间传送信息。该系统还包括耦合到处理逻辑的监视逻辑，并且包括与系统的预定安全级别相关联的一系列地址。监视逻辑获得与该信息相关联的地址。如果当前安全级别与预定安全级别匹配，并且如果地址不对应于地址范围，则监视逻辑限制系统的使用。

10. 发明授权

US09740887B2 Methods and systems to restrict usage of a DMA channel 有权
公开(公告)号：US09740887B2
公开(公告)日：2017-08-22
申请号：US11557298
申请日：2006-11-07
申请人： Gregory R. Conti
发明人： Gregory R. Conti
IPC分类号： G06F13/28 , G06F21/85
CPC分类号： G06F21/85
摘要： In at least some embodiments, a system comprises a processor and a direct memory access (DMA) subsystem coupled to the processor. The system further comprises a component coupled to the DMA subsystem via an interconnect employing security rules, wherein, if the component requests a DMA channel, the DMA subsystem restricts usage of the DMA channel based on the security rules.

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