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1. 发明授权

US06927476B2 Bipolar device having shallow junction raised extrinsic base and method for making the same 失效
标题翻译：具有浅结的双极器件提出外在基极及其制造方法
公开(公告)号：US06927476B2
公开(公告)日：2005-08-09
申请号：US09962738
申请日：2001-09-25
申请人： Gregory G. Freeman , Seshadri Subbanna , Basanth Jagannathan , Kathryn T. Schonenberg , Shwu-Jen Jeng , Kenneth J. Stein , Jeffrey B. Johnson
发明人： Gregory G. Freeman , Seshadri Subbanna , Basanth Jagannathan , Kathryn T. Schonenberg , Shwu-Jen Jeng , Kenneth J. Stein , Jeffrey B. Johnson
IPC分类号： H01L21/331 , H01L29/10 , H01L29/737 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/7378
摘要： A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing. The heterojunction bipolar transistor simultaneously improves three factors that affect the speed and performance of bipolar transistors: base width, base resistance, and base-collector capacitance.
摘要翻译：本文公开了一种凸起的外在基极，硅锗（SiGe）异质结双极晶体管（HBT）及其制造方法。异质结双极晶体管包括基板，形成在基板上的硅锗层，形成在基板上的集电极层，形成在硅锗层上的升高的非本征基极层和形成在硅锗层上的发射极层。硅锗层在发射极层和凸起的非本征基极层之间形成异质结。双极晶体管还包括形成在凸起的非本征基极层的一部分上的基极，在集电极层的一部分上形成的集电极，以及形成在发射极层的一部分上的发射极。因此，异质结双极晶体管包括自对准凸起的外在基极，最小结深度以及影响基底宽度的最小间隙缺陷，全部以最小的热处理形成。异质结双极晶体管同时改善了影响双极晶体管速度和性能的三个因素：基极宽度，基极电阻和基极集电极电容。

2. 发明授权

US06780695B1 BiCMOS integration scheme with raised extrinsic base 有权
标题翻译： BiCMOS整合方案具有突出的外在基础
公开(公告)号：US06780695B1
公开(公告)日：2004-08-24
申请号：US10249563
申请日：2003-04-18
申请人： Huajie Chen , Seshadri Subbanna , Basanth Jagannathan , Gregory G. Freeman , David C. Ahlgren , David Angell , Kathryn T. Schonenberg , Kenneth J. Stein , Fen F. Jamin
发明人： Huajie Chen , Seshadri Subbanna , Basanth Jagannathan , Gregory G. Freeman , David C. Ahlgren , David Angell , Kathryn T. Schonenberg , Kenneth J. Stein , Fen F. Jamin
IPC分类号： H01L218238
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area. At least one bipolar transistor having a raised extrinsic base is then formed in the at least one opening.
摘要翻译：提供一种形成具有凸起的外在基极的BiCMOS集成电路的方法。该方法包括首先在位于具有用于形成至少一个双极晶体管的器件区域的衬底的顶部的栅极电介质的表面上方形成多晶硅层，以及用于形成至少一个互补金属氧化物半导体（CMOS）晶体管的器件区域）。然后将多晶硅层图案化以在器件区域上提供用于形成至少一个双极晶体管及其周围区域的牺牲多晶硅层，同时在用于形成至少一个CMOS晶体管的器件区域中提供至少一个栅极导体。然后围绕至少一个栅极导体的每一个形成至少一对间隔物，然后选择性地去除双极器件区域上的牺牲多晶硅层的一部分以在双极器件区域中提供至少一个开口。然后在至少一个开口中形成至少一个具有凸起的非本征基极的双极晶体管。

3. 发明授权

US06506656B2 Stepped collector implant and method for fabrication 失效
公开(公告)号：US06506656B2
公开(公告)日：2003-01-14
申请号：US09811859
申请日：2001-03-19
申请人： Gregory G. Freeman , Basanth Jagannathan , Shwu-Jen Jeng , Jeffrey B. Johnson
发明人： Gregory G. Freeman , Basanth Jagannathan , Shwu-Jen Jeng , Jeffrey B. Johnson
IPC分类号： H01L21331
CPC分类号： H01L29/66287 , H01L29/0821 , H01L29/36 , H01L29/66242
摘要： The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance with a stepped collector dopant profile that reduces emitter-collector transit time and parasitic resistance with minimal increase in parasitic capacitances. The preferred stepped collector dopant profile includes a shallow implant and a deeper implant. The shallow implant reduces the base-collector space-charge region width, reduce resistance, and tailors the collector-base breakdown characteristics. The deeper implant links the buried collector to the subcollector and provides a low resistance path to the subcollector. The stepped collector dopant profile has minimal impact on the collector-base capacitance outside the intrinsic region of the device since the higher dopant is compensated by, or buried in, the extrinsic base dopants outside the intrinsic region.

4. 发明授权

US06787427B2 Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics 有权
标题翻译：制造具有受控电流增益和改进的击穿电压特性的SiGe HBT的方法
公开(公告)号：US06787427B2
公开(公告)日：2004-09-07
申请号：US10676171
申请日：2003-10-01
申请人： David R. Greenberg , Basanth Jagannathan , Shwu-Jen Jeng , Joseph T. Kocis , Samuel C. Ramac , David M. Rockwell
发明人： David R. Greenberg , Basanth Jagannathan , Shwu-Jen Jeng , Joseph T. Kocis , Samuel C. Ramac , David M. Rockwell
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.
摘要翻译：提供一种制造SiGe异质结双极晶体管（HBT）的方法，其导致具有可控电流增益和改善的击穿电压的SiGe HBT。具有这些特性的SiGe HBT通过在图案化的SiGe基底结构顶上形成原位P掺杂的发射极层来制造。原位P掺杂发射极层是原位P掺杂的a：Si和原位P掺杂多晶硅的双层。包括上述双层发射体的SiGe HBT结构也在此描述。

5. 发明授权

US06656809B2 Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics 失效
标题翻译：制造具有受控电流增益和改进的击穿电压特性的SiGe HBT的方法
公开(公告)号：US06656809B2
公开(公告)日：2003-12-02
申请号：US10047975
申请日：2002-01-15
申请人： David R. Greenberg , Basanth Jagannathan , Shwu-Jen Jeng , Joseph T. Kocis , Samuel C. Ramac , David M. Rockwell
发明人： David R. Greenberg , Basanth Jagannathan , Shwu-Jen Jeng , Joseph T. Kocis , Samuel C. Ramac , David M. Rockwell
IPC分类号： G01R3126
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.
摘要翻译：提供一种制造SiGe异质结双极晶体管（HBT）的方法，其导致具有可控电流增益和改善的击穿电压的SiGe HBT。具有这些特性的SiGe HBT通过在图案化的SiGe基底结构顶上形成原位P掺杂的发射极层来制造。原位P掺杂发射极层是原位P掺杂的a：Si和原位P掺杂多晶硅的双层。包括上述双层发射体的SiGe HBT结构也在此描述。

6. 发明授权

US06744079B2 Optimized blocking impurity placement for SiGe HBTs 有权
标题翻译：优化SiGe HBT的阻塞杂质位置
公开(公告)号：US06744079B2
公开(公告)日：2004-06-01
申请号：US09683983
申请日：2002-03-08
申请人： Basanth Jagannathan , Alvin J. Joseph , Xuefeng Liu , Kathryn T. Schonenberg , Ryan W. Wuthrich
发明人： Basanth Jagannathan , Alvin J. Joseph , Xuefeng Liu , Kathryn T. Schonenberg , Ryan W. Wuthrich
IPC分类号： H01L31072
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/161 , H01L29/7378
摘要： A high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20% and a boron-doped base region formed therein having a thickness. The base region includes diffusion-limiting impurities substantially throughout its thickness, at a peak concentration below that of boron in the base region. Both the base region and the diffusion-limiting impurities are positioned relative to a peak concentration of Ge in the SiGe layer so as to optimize both performance and yield.
摘要翻译：具有峰值Ge浓度至少为20％的SiGe层和其中形成有硼掺杂基底区域的高性能SiGe HBT具有厚度。碱性区域在其整个厚度上基本上包括扩散限制性杂质，峰值浓度低于碱性区域中硼的峰值浓度。碱性区域和扩散限制杂质都相对于SiGe层中的Ge的峰值浓度定位，以便优化性能和产率。

7. 发明授权

US06858532B2 Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling 失效
标题翻译：用于双极晶体管和相关工具的低缺陷预发射极和预基底氧化物蚀刻
公开(公告)号：US06858532B2
公开(公告)日：2005-02-22
申请号：US10316211
申请日：2002-12-10
申请人： Wesley C. Natzle , David C. Ahlgren , Steven G. Barbee , Marc W. Cantell , Basanth Jagannathan , Louis D. Lanzerotti , Seshadri Subbanna , Ryan W. Wuthrich
发明人： Wesley C. Natzle , David C. Ahlgren , Steven G. Barbee , Marc W. Cantell , Basanth Jagannathan , Louis D. Lanzerotti , Seshadri Subbanna , Ryan W. Wuthrich
IPC分类号： H01L21/302 , H01L21/311 , H01L21/331 , H01L21/8249 , H01L29/732 , H01L21/4763
CPC分类号： H01L29/66242 , H01L21/31116 , H01L21/8249
摘要： An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The insulating TEOS glass provides reduced capacitance and helps to achieve high speed. An apparatus is also described for practicing the disclosed process.
摘要翻译：描述了氧化物蚀刻工艺，其可用于双极SiGe器件中的发射极和基极准备。所采用的低温工艺通过保留绝缘TEOS玻璃的COR蚀刻产生发射极和基极之间的电绝缘。绝缘TEOS玻璃提供降低的电容并有助于实现高速度。还描述了用于实施所公开的方法的装置。

8. 发明授权

US07355221B2 Field effect transistor having an asymmetrically stressed channel region 有权
标题翻译：具有不对称应力通道区域的场效应晶体管
公开(公告)号：US07355221B2
公开(公告)日：2008-04-08
申请号：US10908448
申请日：2005-05-12
申请人： Gregory G. Freeman , Anil K. Chinthakindi , David R. Greenberg , Basanth Jagannathan , Marwan H. Khater , John Pekarik , Xudong Wang
发明人： Gregory G. Freeman , Anil K. Chinthakindi , David R. Greenberg , Basanth Jagannathan , Marwan H. Khater , John Pekarik , Xudong Wang
IPC分类号： H01L29/76
CPC分类号： H01L21/26586 , H01L21/26506 , H01L29/665 , H01L29/66545 , H01L29/66659 , H01L29/7835 , H01L29/7843
摘要： A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.
摘要翻译：提供一种场效应晶体管，其包括其中设置有源极区，沟道区和漏极区的邻接单晶半导体区。沟道区域具有与源极区域共同的边缘作为源极边缘，并且沟道区域还具有与作为漏极边缘的漏极区域共同的边缘。栅极导体覆盖沟道区域。场效应晶体管还包括将源极边缘和漏极边缘的另一个施加不大于第二幅度的应力的第一幅度的应力仅施加到源极边缘和漏极边缘中的一个的结构，其中所述第二幅度具有从零到所述第一幅度的大约一半的值。在特定实施例中，将应力以第一幅度施加到源极边缘，同时零或较小幅度应力施加到漏极边缘。在另一个实施例中，将应力以第一幅度施加到漏极边缘，同时将零或较小的幅度应力施加到漏极边缘。

9. 发明申请

US20060071304A1 STRUCTURE AND LAYOUT OF A FET PRIME CELL 审中-公开
标题翻译： FET母细胞的结构和布局
公开(公告)号：US20060071304A1
公开(公告)日：2006-04-06
申请号：US10711640
申请日：2004-09-29
申请人： Basanth Jagannathan , John Pekarik , Christopher Schnabel
发明人： Basanth Jagannathan , John Pekarik , Christopher Schnabel
IPC分类号： H01L23/552
CPC分类号： H01L29/78 , H01L23/4824 , H01L29/1087
摘要： A structure, apparatus and method for a FET prime cell surrounded by a conductor is provided. The surrounding conductor includes a substrate contact arranged proximate a source of the FET. The surrounding conductor may be a ring substrate contact arranged within the substrate of the FET in electrical communication with elongated sources of the FET. No external contacts are needed to the ring substrate contact because no current flows therethrough while the ring substrate contact may act as a collection source for noise such as stray currents.
摘要翻译：提供了由导体包围的FET素电池的结构，装置和方法。周围导体包括靠近FET的源极布置的衬底接触。周围导体可以是布置在FET的衬底内的环形衬底接触，与FET的细长源电连通。由于没有电流流过其中，环形基板接触可能作为用于诸如杂散电流的噪声的收集源，因此环形基板接触不需要外部接触。

10. 发明申请

US20050145172A1 Single reactor, multi-pressure chemical vapor deposition for semiconductor devices 审中-公开
标题翻译：单反应器，半导体器件的多压化学气相沉积
公开(公告)号：US20050145172A1
公开(公告)日：2005-07-07
申请号：US11057176
申请日：2005-02-15
申请人： Jack Chu , Basanth Jagannathan , Ryan Wuthrich
发明人： Jack Chu , Basanth Jagannathan , Ryan Wuthrich
IPC分类号： C23C16/44 , C23C16/54 , C30B25/08 , C30B25/14 , C23C16/00 , C23C16/24
CPC分类号： C23C16/54 , C23C16/4412 , C30B25/08 , C30B25/14 , Y10T117/10
摘要： An apparatus and method for forming at least a portion of an electronic device include a High Vacuum-Chemical Vapor Deposition (UHV-CVD) system and a Low Pressure-Chemical Vapor Deposition (LPCVD) system using a common reactor. The invention overcomes the problem, of silicon containing wafers being dipped in HF acid prior to CVD processing, and the problem of surface passivation between processes in multiple CVD reactors.
摘要翻译：用于形成电子器件的至少一部分的装置和方法包括使用公共反应器的高真空 - 化学气相沉积（UHV-CVD）系统和低压 - 化学气相沉积（LPCVD）系统。本发明克服了在CVD处理之前将含硅晶片浸入HF酸中的问题，以及在多个CVD反应器中的工艺之间的表面钝化的问题。

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