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1. 发明授权

US07442595B2 Bipolar transistor with collector having an epitaxial Si:C region 失效
标题翻译：具有集电极的双极晶体管具有外延Si：C区域
公开(公告)号：US07442595B2
公开(公告)日：2008-10-28
申请号：US11511047
申请日：2006-08-28
申请人： Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg , Andreas D. Stricker
发明人： Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg , Andreas D. Stricker
IPC分类号： H01L21/337
CPC分类号： H01L29/66068 , H01L29/2003 , H01L29/66242
摘要： A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.
摘要翻译：提供了通过不包括C离子注入的方法将C并入到异质结双极器件的集电极区域中的结构和方法。在本发明中，通过在刻蚀到集电极区域的周边沟槽中外延生长将C引入集电体，以更好地控制碳分布和位置。通过使用沟槽隔离区域将集电极区域和在集电体的中心部分上的图案化层作为掩模来形成沟槽。然后，使用沟槽内部的选择性外延生长Si：C以形成具有清晰且明确界定的边缘的Si：C区域。可以优化深度，宽度和C含量以控制和定制集电极注入扩散并减少寄生C CB的周边分量。

2. 发明授权

US06858485B2 Method for creation of a very narrow emitter feature 失效
标题翻译：用于创建非常窄的发射器特征的方法
公开(公告)号：US06858485B2
公开(公告)日：2005-02-22
申请号：US10249780
申请日：2003-05-07
申请人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
发明人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
IPC分类号： H01L21/331 , H01L29/08 , H01L29/732 , H01L21/8238
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/732
摘要： A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped emitter formed in the surface of the intrinsic base. Form an etch stop dielectric layer over the intrinsic base layer above the collector. Form a base contact layer of a conductive material over the etch stop dielectric layer and the intrinsic base layer. Form a second dielectric layer over the base contact layer. Etch a wide window through the dielectric layer and the base contact layer stopping the etching of the window at the etch stop dielectric layer. Form an island or a peninsula narrowing the wide window leaving at least one narrowed window within the wide window. Form sidewall spacers in the either the wide window or the narrowed window. Fill the windows with doped polysilicon to form an extrinsic emitter. Form an emitter below the extrinsic emitter in the surface of the intrinsic base.
摘要翻译：双重多晶硅自对准双极晶体管具有在掺杂半导体衬底中形成的集电极区域，形成在衬底表面上的本征反掺杂基底和形成在本征基底表面上的掺杂发射极。在收集器上方的本征基底层上形成蚀刻停止介电层。在蚀刻停止介电层和本征基极层上形成导电材料的基底接触层。在基底接触层上形成第二介电层。通过介电层和基底接触层蚀刻宽窗口，停止在蚀刻停止介电层处的窗口的蚀刻。形成一个岛屿或一个半岛，缩小广阔的窗户，在宽阔的窗口内至少留出一个狭窄的窗户。在宽窗口或狭窄的窗户中形成侧壁间隔物。用掺杂多晶硅填充窗口以形成外部发射极。在本征基表面的外部发射极之下形成发射体。

3. 发明授权

US07288827B2 Self-aligned mask formed utilizing differential oxidation rates of materials 有权
标题翻译：使用材料的不同氧化速率形成的自对准掩模
公开(公告)号：US07288827B2
公开(公告)日：2007-10-30
申请号：US10969718
申请日：2004-10-20
申请人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
发明人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
IPC分类号： H01L27/082 , H01L27/102
CPC分类号： H01L29/66242 , H01L21/32105 , Y10S438/911
摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.
摘要翻译：使用不同材料的不同氧化速率形成自对准氧化物掩模。自对准氧化物掩模形成在CVD生长的基底NPN基层上，其牺牲了场上的活性区域上的单晶Si（或Si / SiGe）和多晶Si（或Si / SiGe）。通过利用多晶硅（或Si / SiGe）比单晶Si（或Si / SiGe）更快地氧化的事实来制造自对准掩模。通过使用热氧化工艺在多晶硅（或Si / siGe）和单晶Si（或Si / siGe）上形成氧化膜，以在多晶硅（或Si / SiGe）上形成厚的氧化层，以及在单晶Si（或Si / siGe）上方的薄氧化层，随后进行受控氧化物蚀刻以除去单晶Si（或Si / siGe）上的薄氧化层，同时将自对准氧化物掩模层留在多晶硅（或Si / siGe）。然后在自对准掩模形成之后形成隆起的外在基体。该自对准氧化物掩模阻挡从扩展的外在碱基到收集器角的扩散。

4. 发明授权

US07180157B2 Bipolar transistor with a very narrow emitter feature 失效
标题翻译：双极晶体管具有非常窄的发射极特性
公开(公告)号：US07180157B2
公开(公告)日：2007-02-20
申请号：US10978775
申请日：2004-11-01
申请人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
发明人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
IPC分类号： H01L27/082
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/732
摘要： A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped intrinsic emitter formed in the surface of the intrinsic base. An etch stop insulator layer overlies the intrinsic base layer above the collector. A base contact layer of a conductive material overlies the etch stop dielectric layer and the intrinsic base layer. A dielectric layer overlies the base contact layer. A wide window extends through the insulator layer and the base contact layer down to the insulator layer. An island or a peninsula is formed in the wide window leaving at least one narrowed window within the wide window, with sidewall spacers in either the wide window or the narrowed window. The narrowed windows are filled with doped polysilicon forming an extrinsic emitter with the intrinsic emitter formed below the extrinsic emitter in the surface of the intrinsic base.
摘要翻译：双重多晶硅，自对准双极晶体管具有在掺杂半导体衬底中形成的集电极区域，形成在衬底表面上的本征反掺杂基底和形成在本征基底表面的掺杂本征发射极。蚀刻停止绝缘体层覆盖在收集器上方的本征基极层。导电材料的基极接触层覆盖在蚀刻停止介电层和本征基极层之间。电介质层覆盖在基底接触层上。宽窗口延伸穿过绝缘体层和基底接触层向下延伸到绝缘体层。在宽窗口中形成岛或半岛，在宽窗口内留下至少一个变窄的窗口，在宽窗口或狭窄窗口中具有侧壁间隔物。变窄的窗口填充有掺杂的多晶硅，其形成外部发射极，本征发射极在本征基极表面的外部发射极之下形成。

5. 发明授权

US06844225B2 Self-aligned mask formed utilizing differential oxidation rates of materials 失效
标题翻译：使用材料的不同氧化速率形成的自对准掩模
公开(公告)号：US06844225B2
公开(公告)日：2005-01-18
申请号：US10345469
申请日：2003-01-15
申请人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
发明人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
IPC分类号： H01L21/321 , H01L21/331 , H01L29/732 , H01L29/737 , H01L21/00
CPC分类号： H01L29/66242 , H01L21/32105 , Y10S438/911
摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.
摘要翻译：使用不同材料的不同氧化速率形成自对准氧化物掩模。自对准氧化物掩模形成在CVD生长的基底NPN基层上，其牺牲了场上的活性区域上的单晶Si（或Si / SiGe）和多晶Si（或Si / SiGe）。通过利用多晶硅（或Si / SiGe）比单晶Si（或Si / SiGe）更快地氧化的事实来制造自对准掩模。通过使用热氧化工艺在多晶硅（或Si / siGe）和单晶Si（或Si / siGe）上形成氧化膜，以在多晶硅（或Si / SiGe）上形成厚的氧化层，以及在单晶Si（或Si / siGe）上方的薄氧化层，随后进行受控氧化物蚀刻以除去单晶Si（或Si / siGe）上的薄氧化层，同时将自对准氧化物掩模层留在多晶硅（或Si / siGe）。然后在自对准掩模形成之后形成隆起的外在基体。该自对准氧化物掩模阻挡从扩展的外在碱基到收集器角的扩散。

6. 发明授权

US07888745B2 Bipolar transistor with dual shallow trench isolation and low base resistance 有权
标题翻译：具有双浅沟槽隔离和低基极电阻的双极晶体管
公开(公告)号：US07888745B2
公开(公告)日：2011-02-15
申请号：US11425550
申请日：2006-06-21
申请人： Marwan H. Khater , Andreas D. Stricker , Bradley A. Orner , Mattias E. Dahlstrom
发明人： Marwan H. Khater , Andreas D. Stricker , Bradley A. Orner , Mattias E. Dahlstrom
IPC分类号： H01L29/72
CPC分类号： H01L29/7378 , H01L29/66242
摘要： An improved bipolar transistor with dual shallow trench isolation for reducing the parasitic component of the base to collector capacitance Ccb and base resistance Rb is provided. The structure includes a semiconductor substrate having at least a pair of neighboring first shallow trench isolation (STI) regions disposed therein. The pair of neighboring first STI regions defines an active area in the substrate. The structure also includes a collector disposed in the in the active area of the semiconductor substrate, a base layer disposed atop a surface of the semiconductor substrate in the active area, and a raised extrinsic base disposed on the base layer. In accordance with the present, the raised extrinsic base has an opening to a portion of the base layer. An emitter is located in the opening and extending on a portion of the patterned raised extrinsic base; the emitter is spaced apart and isolated from the raised extrinsic base. Moreover, and in addition to the first STI region, a second shallow trench isolation (STI) region is present in the semiconductor substrate which extends inward from each pair of said first shallow trench isolation regions towards said collector. The second STI region has an inner sidewall surface that is sloped. In some embodiments, the base is completely monocrystalline.
摘要翻译：提供了具有双浅沟槽隔离的改进的双极晶体管，用于减小基极与集电极电容Ccb和基极电阻Rb的寄生分量。该结构包括具有设置在其中的至少一对相邻的第一浅沟槽隔离（STI）区域的半导体衬底。该对相邻的第一STI区域限定衬底中的有源区域。该结构还包括设置在半导体衬底的有源区域中的集电体，设置在有源区域中的半导体衬底的表面上的基极层和设置在基极层上的凸起的非本征基极。根据本发明，凸起的外在基部具有对基底层的一部分的开口。发射器位于开口中并在图案化的凸起的外基极的一部分上延伸; 发射极间隔开并与凸起的外基极隔离。而且，除了第一STI区之外，第二浅沟槽隔离（STI）区域存在于从每对所述第一浅沟槽隔离区向内朝向所述集电极延伸的半导体衬底中。第二STI区域具有倾斜的内侧壁表面。在一些实施方案中，碱是完全单晶的。

7. 发明申请

US20080268604A1 METHODS OF BASE FORMATION IN A BiCMOS PROCESS 失效
标题翻译： BiCMOS工艺中基质形成的方法
公开(公告)号：US20080268604A1
公开(公告)日：2008-10-30
申请号：US12128077
申请日：2008-05-28
申请人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
发明人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

8. 发明授权

US07390721B2 Methods of base formation in a BiCMOS process 失效
标题翻译： BiCMOS工艺中碱形成的方法
公开(公告)号：US07390721B2
公开(公告)日：2008-06-24
申请号：US11231385
申请日：2005-09-21
申请人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
发明人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

9. 发明授权

US07696034B2 Methods of base formation in a BiCOMS process 失效
标题翻译： BiCOMS工艺中碱形成的方法
公开(公告)号：US07696034B2
公开(公告)日：2010-04-13
申请号：US12128077
申请日：2008-05-28
申请人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , Beth Ann Rainey , Jae-Sung Rieh , Andreas D. Stricker
发明人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , Beth Ann Rainey , Jae-Sung Rieh , Andreas D. Stricker
IPC分类号： H01L21/8238
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

10. 发明授权

US07253096B2 Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same 失效
标题翻译：双极晶体管具有可选择的自对准的外部基极和其形成方法
公开(公告)号：US07253096B2
公开(公告)日：2007-08-07
申请号：US11289915
申请日：2005-11-30
申请人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
发明人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
IPC分类号： H01L21/4763
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.
摘要翻译：公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。然后通过在第一非本征基层上的光刻形成电介质着色焊盘。接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

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