专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5253357A System for determining pluggable memory characteristics employing a status register to provide information in response to a preset field of an address 失效
标题翻译：用于确定可插拔存储器特性的系统，其采用状态寄存器来提供响应于地址的预设字段的信息
公开(公告)号：US5253357A
公开(公告)日：1993-10-12
申请号：US715077
申请日：1991-06-13
申请人： Greg L. Allen , Jae-Hu Kim , Lynn R. Watson
发明人： Greg L. Allen , Jae-Hu Kim , Lynn R. Watson
IPC分类号： G06F12/06
CPC分类号： G06F12/0684
摘要： A system is described that includes an arithmetic logic unit that senses the presence of a circuit module in a connector, wherein one type of circuit module, if present, automatically provides a set of signals on a predetermined pin set that indicates characteristics of the circuit module. The system also includes circuitry that enables the determination of the presence of other types of pluggable circuit modules in the connector. The circuitry comprises a latch circuit for holding a received address for the circuit module. In the received address, a preset field of bits is present which identifies a field in a status register. The status register stores n fields of information defining the characteristics of the pluggable circuit module and is responsive to the preset field of bits to provide signals on the predetermined pin set indicating the information.

2. 发明授权

US07002254B2 Integrated circuit package employing flip-chip technology and method of assembly 失效
公开(公告)号：US07002254B2
公开(公告)日：2006-02-21
申请号：US10636993
申请日：2003-08-06
申请人： Timothy V. Harper , Greg L. Allen
发明人： Timothy V. Harper , Greg L. Allen
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/05568 , H01L2224/05573 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06589 , H01L2924/00014 , H01L2924/15151 , H01L2924/15153 , H01L2924/15165 , H05K1/183 , H01L2924/00 , H01L2224/05599
摘要： An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

3. 发明申请

US20150012675A1 METHODS AND APPARATUS FOR INTERFACING A HOST DEVICE TO A PERIPHERAL DEVICE IN ORDER TO INCREASE CONSUMPTION OF CONSUMABLE PRODUCTS BY THE PERIPHERAL DEVICE 有权
标题翻译：用于将主机设备连接到外围设备的方法和装置，以增加外围设备消耗的产品的消耗
公开(公告)号：US20150012675A1
公开(公告)日：2015-01-08
申请号：US13935104
申请日：2013-07-03
申请人： Gary D. Zimmerman , J. Daren Bledsoe , Lyman Leonard Hall , Mark D. Montierth , Greg L. Allen
发明人： Gary D. Zimmerman , J. Daren Bledsoe , Lyman Leonard Hall , Mark D. Montierth , Greg L. Allen
IPC分类号： G06F3/12
CPC分类号： G06F3/1293 , G06F3/1209 , G06F3/1236 , G06F3/1237 , G06F3/1288
摘要： Some of the embodiments of the present disclosure provide a method comprising providing an apparatus, wherein the apparatus is configured to be coupled to (i) a peripheral device and (ii) a host device. The apparatus includes memory configured to store logic, wherein the logic is configured to (i) allow the host device and the peripheral device to communicate with each other and (ii) operate the peripheral device. The apparatus further includes a processor configured to execute the logic. The method further comprises bundling the apparatus with a consumable product for sale with the consumable product, wherein the consumable product is configured to be consumed by the peripheral device.
摘要翻译：本公开的一些实施例提供了一种包括提供装置的方法，其中所述装置被配置为耦合到（i）外围设备和（ii）主机设备。所述设备包括被配置为存储逻辑的存储器，其中所述逻辑被配置为（i）允许所述主机设备和所述外围设备彼此通信，以及（ii）操作所述外围设备。该装置还包括配置成执行逻辑的处理器。所述方法还包括将所述设备与所述消耗品一起销售的消耗品捆绑，其中所述消耗品被配置为被所述外围设备消耗。

4. 发明授权

US06659512B1 Integrated circuit package employing flip-chip technology and method of assembly 有权
标题翻译：集成电路封装采用倒装芯片技术和组装方法
公开(公告)号：US06659512B1
公开(公告)日：2003-12-09
申请号：US10199441
申请日：2002-07-18
申请人： Timothy V. Harper , Greg L. Allen
发明人： Timothy V. Harper , Greg L. Allen
IPC分类号： H01L2940
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/05568 , H01L2224/05573 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06589 , H01L2924/00014 , H01L2924/15151 , H01L2924/15153 , H01L2924/15165 , H05K1/183 , H01L2924/00 , H01L2224/05599
摘要： An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.
摘要翻译：集成电路封装包括具有第一表面的封装基板，第一表面包括第一阵列的互连位置和第二互连位置阵列。第一集成电路管芯具有包括互连位置阵列的第一表面。第二集成电路管芯具有包括互连位置阵列的第一表面。互连点的第一阵列电连接到第二集成电路管芯的互连点阵列。互连点的第二阵列电连接到第一集成电路管芯的互连位置的阵列。第一集成电路管芯位于封装衬底和第二集成电路管芯内。

5. 发明授权

US5444827A Method and apparatus for preventing print overruns by rasterizing complex page strips using an increased clock frequency 失效
标题翻译：用于通过使用增加的时钟频率光栅化复杂页面条来防止打印超限的方法和装置
公开(公告)号：US5444827A
公开(公告)日：1995-08-22
申请号：US247806
申请日：1994-05-23
申请人： Randall D. Briggs , Greg L. Allen
发明人： Randall D. Briggs , Greg L. Allen
IPC分类号： B41J5/30 , G06F3/12 , G06K15/00 , G06K15/12
CPC分类号： G06K15/12 , G06K15/1823 , G06K15/1848 , G06K2215/0082
摘要： A page printer includes a variable frequency clock for producing at least two clock frequencies, one higher than the other. The page printer includes a first memory for storing a page processing procedure and a second memory for storing data comprising full page strips. A processor operates at the first clock frequency in conjunction with the page processing procedure and derives a rasterization execution time (RET) for display commands that define images to be printed in each page strip of a page. The processor compares the RET for each page strip with a threshold value and rasterizes in the standard manner any page strip whose RET is equal to or less than the threshold value (while operating under the influence of the first clock frequency). When a complex page strip is found (whose RET exceeds the threshold), the variable frequency clock is controlled to generate a second higher frequency clock signal and to cause the processor to operate at a rate determined by the higher clock frequency so that display commands in the complex page strip are rasterized at higher speed.
摘要翻译：页面打印机包括用于产生至少两个时钟频率的可变频率时钟，一个高于另一个。页面打印机包括用于存储页面处理过程的第一存储器和用于存储包括全页条带的数据的第二存储器。处理器在第一时钟频率下与页面处理过程一起操作，并且导出用于定义要在页面的每个页面条中打印的图像的显示命令的光栅化执行时间（RET）。处理器将每个页面条的RET与阈值进行比较，并以标准方式栅格其RET等于或小于阈值（同时在第一个时钟频率的影响下工作）的任何页面条。当发现复杂的页面条（其RET超过阈值）时，控制可变频率时钟以产生第二较高频率时钟信号，并使处理器以由较高时钟频率确定的速率工作，使得显示命令复杂的页面条以更高的速度进行光栅化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式