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1. 发明授权

US06020611A Semiconductor component and method of manufacture 失效
标题翻译：半导体元件及制造方法
公开(公告)号：US06020611A
公开(公告)日：2000-02-01
申请号：US95504
申请日：1998-06-10
申请人： Gordon C. Ma , Christopher P. Dragon
发明人： Gordon C. Ma , Christopher P. Dragon
IPC分类号： H01L21/336 , H01L29/08 , H01L29/78
CPC分类号： H01L29/66659 , H01L29/7835 , H01L29/0847
摘要： A semiconductor component includes a substrate (101), an electrode (105) located over the substrate (101), a heavily doped region (542) located in the substrate (101) and self-aligned to the electrode (105), an other heavily doped region (543) located in the substrate (101), a lightly doped region (422) located in the substrate (101) between the heavily doped regions (542, 543) and self-aligned to the electrode (105), and another lightly doped region (432) located in the substrate (101) between the lightly doped region (422) and the other heavily doped region (543).
摘要翻译：半导体部件包括衬底（101），位于衬底（101）上方的电极（105），位于衬底（101）中并与电极（105）自对准的重掺杂区域（542），另一个位于衬底（101）中的重掺杂区域（543），位于重掺杂区域（542,543）之间并与电极（105）自对准的衬底（101）中的轻掺杂区域（422），以及位于轻掺杂区域（422）和另一个重掺杂区域（543）之间的衬底（101）中的另一个轻掺杂区域（432）。

2. 发明授权

US5371394A Double implanted laterally diffused MOS device and method thereof 失效
标题翻译：双向植入横向扩散MOS器件及其方法
公开(公告)号：US5371394A
公开(公告)日：1994-12-06
申请号：US153503
申请日：1993-11-15
申请人： Gordon C. Ma , Hassan Pirastehfar , Steven J. Adler
发明人： Gordon C. Ma , Hassan Pirastehfar , Steven J. Adler
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L29/68 , H01L21/04
CPC分类号： H01L29/66659 , H01L29/1045 , H01L29/1083 , H01L29/7835
摘要： An NMOS transistor has a source and a drain composed of n+ type of semiconductor material. A substrate region composed of a p type of semiconductor material is disposed between the source and the drain. A gate region is disposed above the substrate region and between the source region and the drain region. A first implant region is disposed adjacent to the source region and the gate region. The first implant region is composed of p type of semiconductor material with a first doping concentration. A second implant region is disposed between the first implant region and the substrate. The second implant region is composed of p type of semiconductor material with a second doping concentration. The channel doping profile first and second implant regions is tailored to obtain the optimum internal electric field to maximize device transconductance, while simultaneously controlling the device threshold voltage and punch through characteristics.
摘要翻译： NMOS晶体管具有由n +型半导体材料构成的源极和漏极。由p型半导体材料构成的衬底区域设置在源极和漏极之间。栅极区域设置在衬底区域之上并且在源极区域和漏极区域之间。第一注入区域邻近源极区域和栅极区域设置。第一注入区域由具有第一掺杂浓度的p型半导体材料组成。第二植入区域设置在第一植入区域和基底之间。第二注入区由具有第二掺杂浓度的p型半导体材料组成。沟道掺杂分布第一和第二注入区域被定制以获得最佳内部电场以最大化器件跨导，同时控制器件阈值电压和穿透特性。

3. 发明授权

US06734728B1 RF power transistor with internal bias feed 有权
标题翻译：具有内部偏置馈电的RF功率晶体管
公开(公告)号：US06734728B1
公开(公告)日：2004-05-11
申请号：US10324694
申请日：2002-12-19
申请人： Larry Leighton , Prasanth Perugupalli , Nagaraj V. Dixit , Gordon C. Ma
发明人： Larry Leighton , Prasanth Perugupalli , Nagaraj V. Dixit , Gordon C. Ma
IPC分类号： H03F304
CPC分类号： H01L23/66 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2223/6644 , H01L2223/665 , H01L2224/48091 , H01L2224/49175 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01073 , H01L2924/1306 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H03F3/14 , H03F3/195 , H03F3/604 , H01L2924/00 , H01L2224/45099
摘要： Conventional broadband RF power amplifiers use a ¼ wavelength transmission line to decouple the gate bias DC source from the gate circuitry and a second ¼ wavelength transmission line to decouple the drain bias DC source from the drain circuitry, taking up considerable printed circuit board space. A novel broadband RF power amplifier uses a transistor with separate terminals for injection of gate bias and drain bias DC sources, eliminating the need for ¼ wavelength transmission lines, thereby freeing up space and allowing higher density packaging. The power amplifier transistor can be implemented with a single die circuit or multiple die circuits operating in parallel.
摘要翻译：传统的宽带射频功率放大器使用1/4波长传输线来将栅极偏置DC源与栅极电路和第二个1/4波长传输线去耦，从而将漏极偏置DC源与漏极电路分离，占据相当大的印刷电路板空间。一种新颖的宽带射频功率放大器使用具有单独端子的晶体管，用于注入栅极偏置和漏极偏置直流电源，无需使用1/4波长传输线，从而释放空间并允许更高密度的封装。功率放大器晶体管可以用单个晶片电路或并行工作的多个管芯电路来实现。

4. 发明授权

US06271106B1 Method of manufacturing a semiconductor component 有权
标题翻译：制造半导体部件的方法
公开(公告)号：US06271106B1
公开(公告)日：2001-08-07
申请号：US09430725
申请日：1999-10-29
申请人： Gordon M. Grivna , Richard A. Keating , Gordon C. Ma
发明人： Gordon M. Grivna , Richard A. Keating , Gordon C. Ma
IPC分类号： H01L2144
CPC分类号： H01L21/76802 , H01L29/66545
摘要： A method of manufacturing a semiconductor component includes sequentially disposing a first electrically conductive layer (130), a dielectric layer (140), and a sacrificial layer (150) over a substrate (110). An etch mask is used to defined a gate stack (210) comprised of the sacrificial layer (150), the dielectric layer, and the first electrically conductive layer. Another dielectric layer (310) is deposited over the substrate (110) and the gate stack (210). This second dielectric layer (310) is planarized to expose the sacrificial layer (150). The sacrificial layer (150) of the gate stack (210) and the dielectric layer (140) of the gate stack (210) are sequentially removed, and another electrically conductive layer (740) is deposited over the first electrically conductive layer of the gate stack to form a gate electrode made of, among other features, two electrically conductive layers.
摘要翻译：制造半导体部件的方法包括在衬底（110）上顺序地设置第一导电层（130），电介质层（140）和牺牲层（150）。蚀刻掩模用于限定由牺牲层（150），电介质层和第一导电层组成的栅极堆叠（210）。在衬底（110）和栅极叠层（210）上方沉积另一介质层（310）。该第二介电层（310）被平坦化以暴露牺牲层（150）。栅堆叠（210）的牺牲层（150）和栅堆叠（210）的电介质层（140）被顺序地去除，另一导电层（740）沉积在栅极的第一导电层上堆叠以形成除了其它特征之外由两个导电层制成的栅电极。

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