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1. 发明申请

US20070006116A1 Method for real time monitoring and verifying optical proximity correction model and method 有权
标题翻译：用于实时监测和验证光学邻近校正模型和方法的方法
公开(公告)号：US20070006116A1
公开(公告)日：2007-01-04
申请号：US11169616
申请日：2005-06-30
申请人： Gokhan Percin , Ram Ramanujam , Franz Zach , Koichi Suzuki
发明人： Gokhan Percin , Ram Ramanujam , Franz Zach , Koichi Suzuki
IPC分类号： G06F17/50
CPC分类号： G03F1/84 , G03F1/36 , G03F1/44 , G03F7/70441 , G03F7/70683
摘要： This invention relates to a method for real time monitoring and verifying optical proximity correction (OPC) models and methods in production. Prior to OPC is performed on the integrated circuit layout, a model describing the optical, physical and chemical processes involving lithography should be obtained accurately and precisely. In general, the model is calibrated using the measurements obtained by running wafers through the same lithography, patterning, and etch processes. In this invention, a novel real time method for verifying and monitoring the calibrated model on a production or monitor wafer is presented: optical proximity corrected (OPC-ed) test and verification structures are placed on scribe lines or cut lines of the production or monitor wafer, and with pre-determined schedule, the critical dimensions and images of these test and verification structures are monitored across wafer and across exposure field.
摘要翻译：本发明涉及一种用于实时监测和验证生产中的光学邻近校正（OPC）模型和方法的方法。在对集成电路布局进行OPC之前，应准确准确地描述涉及光刻的光学，物理和化学过程的模型。通常，使用通过相同的光刻，图案化和蚀刻工艺运行晶片获得的测量来校准模型。在本发明中，提出了一种用于在生产或监控晶圆上验证和监测校准模型的新型实时方法：将光学邻近校正（OPC-ed）测试和验证结构放置在生产或监视器的划线或切割线上晶圆，并且具有预定的时间表，这些测试和验证结构的关键尺寸和图像在晶片和曝光场之间进行监测。

2. 发明申请

US20060266243A1 Calibration on wafer sweet spots 有权
标题翻译：校准晶圆甜点
公开(公告)号：US20060266243A1
公开(公告)日：2006-11-30
申请号：US11139551
申请日：2005-05-31
申请人： Gokhan Percin , Ram Ramanujam , Franz Zach , Abdurrahman Sezginer , Chi-Song Horng , Roy Prasad
发明人： Gokhan Percin , Ram Ramanujam , Franz Zach , Abdurrahman Sezginer , Chi-Song Horng , Roy Prasad
IPC分类号： B41F33/00 , B41F1/54
CPC分类号： G03F7/70441 , G03F1/36 , G03F1/44 , G03F1/68
摘要： A method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips. More particularly, a method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips based on the parameters of test patterns measured at the “wafer sweet spots” so as to arrive at an accurate model.
摘要翻译：提供了一种产生OPC模型的方法，其考虑了在制造半导体芯片的过程中发生的跨晶片变化。更具体地，提供了一种用于生成OPC模型的方法，其考虑了在基于在“晶片甜点”处测量的测试图案的参数的制造半导体芯片的过程期间发生的跨晶片变化，以便到达准确模型。

3. 发明申请

US20060282814A1 Method for verifying and choosing lithography model 有权
公开(公告)号：US20060282814A1
公开(公告)日：2006-12-14
申请号：US11141805
申请日：2005-05-31
申请人： Gokhan Percin , Ram Ramanujam , Franz Zach
发明人： Gokhan Percin , Ram Ramanujam , Franz Zach
IPC分类号： G06F17/50
CPC分类号： G03F7/70616 , G03F7/705 , G03F7/70516
摘要： A test mask with both verification structures and calibration structures is provided to enable the formation of an image of at least one verification structure and at least one calibration structure at a plurality of different test site locations under different dose and defocus conditions to allow the calibration structures to be measured and to obtain at least one computational model for optical proximity correction purposes.

4. 发明申请

US20070143733A1 Method of compensating photomask data for the effects of etch and lithography processes 有权
标题翻译：补偿光掩模数据的方法，用于蚀刻和光刻工艺的影响
公开(公告)号：US20070143733A1
公开(公告)日：2007-06-21
申请号：US11541921
申请日：2006-10-02
申请人： Franz Zach , Jesus Carrero , Bayram Yenikaya , Gokhan Percin , Xuelong Cao , Abdurrahman Sezginer
发明人： Franz Zach , Jesus Carrero , Bayram Yenikaya , Gokhan Percin , Xuelong Cao , Abdurrahman Sezginer
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for synthesizing a photomask data set from a given target layout, including the following steps: (a) providing a set of target polygons for the target layout; (b) fitting a smooth curve to a target polygon of the set of target polygons, the curve having a set of etch-target points; (c) moving the etch target points according to a model of an etch process to produce a set of lithography-target points; and (d) synthesizing a photomask data set based on a model of a lithography process and the set of lithography-target points.
摘要翻译：一种用于从给定目标布局合成光掩模数据集的方法，包括以下步骤：（a）为目标布局提供一组目标多边形; （b）将平滑曲线拟合到所述目标多边形集合的目标多边形，所述曲线具有一组蚀刻目标点; （c）根据蚀刻工艺的模型移动蚀刻目标点以产生一组光刻目标点; 以及（d）基于光刻工艺的模型和所述一组光刻目标点合成光掩模数据集。

5. 发明申请

US20060073686A1 Method and system for reducing the impact of across-wafer variations on critical dimension measurements 有权
公开(公告)号：US20060073686A1
公开(公告)日：2006-04-06
申请号：US10971350
申请日：2004-10-22
申请人： Franz Zach , Abdurrahman Sezginer , Gokhan Percin
发明人： Franz Zach , Abdurrahman Sezginer , Gokhan Percin
IPC分类号： H01L21/22
CPC分类号： G03B27/72 , G03F7/70441 , G03F7/70558 , G03F7/70625 , G03F7/70641
摘要： First and second exposures of a mask onto a wafer are performed such that the exposure field of the second exposure partially overlaps the exposure field of the first exposure. A characteristic of a set of features is determined, and a value of a parameter of an optical proximity correction model is determined. An alignment feature can be used to align a measurement tool. In yet another embodiment, pupil intensity distribution of an imaging system is measured by exposing an image field of a radiation detector with a bright feature, positioning the detector at a distance away from the image plane, and exposing the image field of the detector with a bright feature, resulting in a cumulative exposure of the image field of the detector from the two exposures. A characteristic of a spatial pattern in the cumulative exposure of the image field of the detector is then determined.

6. 发明申请

US20060268254A1 Method for measuring and verifying stepper illumination 有权
标题翻译：步进照明的测量和验证方法
公开(公告)号：US20060268254A1
公开(公告)日：2006-11-30
申请号：US11141803
申请日：2005-05-31
申请人： Gokhan Percin , Abdurrahman Sezginer , Franz Zach
发明人： Gokhan Percin , Abdurrahman Sezginer , Franz Zach
IPC分类号： G03B27/72
CPC分类号： G03F7/7025 , G03F7/70591
摘要： An apparatus and method for characterizing an illumination pupil of an exposure tool comprises forming a plurality of pinhole test patterns at a plurality of test site locations to facilitate locating test pattern edges for extracting therefrom the illumination pupil characteristics of the exposure tool.
摘要翻译：用于表征曝光工具的照明光瞳的装置和方法包括在多个测试位置处形成多个针孔测试图案，以便于定位测试图案边缘以从其中提取曝光工具的照明光瞳特性。

7. 发明申请

US20120187508A1 INTEGRATION OF STRUCTURALLY-STABLE ISOLATED CAPACITIVE MICROMACHINED ULTRASONIC TRANSDUCER (CMUT) ARRAY CELLS AND ARRAY ELEMENTS 有权
标题翻译：结构稳定隔离电容式微超声波超声波传感器（CMUT）阵列单元和阵列元件的集成
公开(公告)号：US20120187508A1
公开(公告)日：2012-07-26
申请号：US13419216
申请日：2012-03-13
申请人： Steven J. Adler , Peter Johnson , Gokhan Percin , Shahram Mostafazadeh
发明人： Steven J. Adler , Peter Johnson , Gokhan Percin , Shahram Mostafazadeh
IPC分类号： H01L29/84 , H01L21/50
CPC分类号： H01L27/1203 , B06B1/0292 , G01N29/2406 , H01L21/76898
摘要： A method for forming a capacitive micromachined ultrasonic transducer (CMUT) includes forming multiple CMUT elements in a first semiconductor-on-insulator (SOI) structure. Each CMUT element includes multiple CMUT cells. The first SOI structure includes a first handle wafer, a first buried layer, and a first active layer. The method also includes forming a membrane over the CMUT elements and forming electrical contacts through the first handle wafer and the first buried layer. The electrical contacts are in electrical connection with the CMUT elements. The membrane could be formed by bonding a second SOI structure to the first SOI structure, where the second SOI structure includes a second handle wafer, a second buried layer, and a second active layer. The second handle wafer and the second buried layer can be removed, and the membrane includes the second active layer.
摘要翻译：一种用于形成电容微加工超声换能器（CMUT）的方法包括在第一绝缘体上绝缘体（SOI）结构中形成多个CMUT元件。每个CMUT元素包括多个CMUT单元。第一SOI结构包括第一处理晶片，第一掩埋层和第一有源层。该方法还包括在CMUT元件上形成膜并通过第一处理晶片和第一掩埋层形成电触点。电触点与CMUT元件电连接。可以通过将第二SOI结构结合到第一SOI结构来形成膜，其中第二SOI结构包括第二处理晶片，第二掩埋层和第二有源层。可以去除第二处理晶片和第二掩埋层，并且膜包括第二有源层。

8. 发明授权

US08222065B1 Method and system for forming a capacitive micromachined ultrasonic transducer 有权
标题翻译：用于形成电容微加工超声换能器的方法和系统
公开(公告)号：US08222065B1
公开(公告)日：2012-07-17
申请号：US12587139
申请日：2009-10-02
申请人： Peter Smeys , Peter Johnson , Gokhan Percin
发明人： Peter Smeys , Peter Johnson , Gokhan Percin
IPC分类号： H01L29/72
CPC分类号： B06B1/0292 , H01L27/0688
摘要： A method for forming a capacitive micromachined ultrasonic transducer (CMUT) is provided that includes forming oxide features outwardly of a CMUT control chip in a silicon wafer. The oxide features are planarized. A silicon-on-insulator (SOI) wafer is bonded to the planarized oxide features. For a particular embodiment, the SOI wafer comprises a single crystal epitaxial layer, a buried oxide layer and a silicon layer, and the single crystal epitaxial layer is bonded to the planarized oxide features, after which the silicon layer and the buried oxide layer of the SOI wafer are removed, leaving the single crystal epitaxial layer bonded to the oxide layer.
摘要翻译：提供一种用于形成电容微加工超声换能器（CMUT）的方法，其包括在硅晶片中的CMUT控制芯片外部形成氧化物特征。氧化物的特征被平坦化。绝缘体上硅（SOI）晶片与平坦化的氧化物特征结合。对于特定实施例，SOI晶片包括单晶外延层，掩埋氧化物层和硅层，并且单晶外延层结合到平坦化的氧化物特征，之后硅层和掩埋氧化物层去除SOI晶片，留下单晶外延层与氧化物层结合。

9. 发明授权

US08279409B1 System and method for calibrating a lithography model 有权
标题翻译：用于校准光刻模型的系统和方法
公开(公告)号：US08279409B1
公开(公告)日：2012-10-02
申请号：US12536425
申请日：2009-08-05
申请人： Abdurrahman Sezginer , Hsu-Ting Huang , Jesus Orsely Carrero , Tatung Chow , Kostyantyn Chuyeshov , Gokhan Percin
发明人： Abdurrahman Sezginer , Hsu-Ting Huang , Jesus Orsely Carrero , Tatung Chow , Kostyantyn Chuyeshov , Gokhan Percin
IPC分类号： G03B27/32 , G03B27/54 , G06F17/50
CPC分类号： G03F1/70 , G03F1/36 , G03F7/70441 , G03F7/705 , G03F7/70516
摘要： The present invention provides a method for calibrating a computational model of a lithography process by calculating a demerit function using an intensity measurement at a location of a wafer; and calibrating the lithography model or a mask making model by determining values of parameters of the computational model using the calculated demerit function. The method may also use a second demerit function that is defined by the sum of squares of differences between a simulated and measured critical dimensions of a feature on the wafer.
摘要翻译：本发明提供了一种用于通过使用在晶片的位置处的强度测量来计算缺点函数来校准光刻处理的计算模型的方法; 并通过使用计算的缺点函数确定计算模型的参数值来校准光刻模型或掩模制作模型。该方法还可以使用由晶片上的特征的模拟和测量的临界尺寸之间的差的平方和定义的第二缺点函数。

10. 发明授权

US08563345B2 Integration of structurally-stable isolated capacitive micromachined ultrasonic transducer (CMUT) array cells and array elements 有权
标题翻译：结构稳定的隔离电容微加工超声波传感器（CMUT）阵列单元和阵列元件的集成
公开(公告)号：US08563345B2
公开(公告)日：2013-10-22
申请号：US13419216
申请日：2012-03-13
申请人： Steven J. Adler , Peter Johnson , Gokhan Percin , Shahram Mostafazadeh
发明人： Steven J. Adler , Peter Johnson , Gokhan Percin , Shahram Mostafazadeh
IPC分类号： H01L29/72
CPC分类号： H01L27/1203 , B06B1/0292 , G01N29/2406 , H01L21/76898
摘要： A method for forming a capacitive micromachined ultrasonic transducer (CMUT) includes forming multiple CMUT elements in a first semiconductor-on-insulator (SOI) structure. Each CMUT element includes multiple CMUT cells. The first SOI structure includes a first handle wafer, a first buried layer, and a first active layer. The method also includes forming a membrane over the CMUT elements and forming electrical contacts through the first handle wafer and the first buried layer. The electrical contacts are in electrical connection with the CMUT elements. The membrane could be formed by bonding a second SOI structure to the first SOI structure, where the second SOI structure includes a second handle wafer, a second buried layer, and a second active layer. The second handle wafer and the second buried layer can be removed, and the membrane includes the second active layer.
摘要翻译：一种用于形成电容微加工超声换能器（CMUT）的方法包括在第一绝缘体上绝缘体（SOI）结构中形成多个CMUT元件。每个CMUT元素包括多个CMUT单元。第一SOI结构包括第一处理晶片，第一掩埋层和第一有源层。该方法还包括在CMUT元件上形成膜并通过第一处理晶片和第一掩埋层形成电触点。电触点与CMUT元件电连接。可以通过将第二SOI结构结合到第一SOI结构来形成膜，其中第二SOI结构包括第二处理晶片，第二掩埋层和第二有源层。可以去除第二处理晶片和第二掩埋层，并且膜包括第二有源层。

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