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1. 发明授权

US07002399B2 Basic stage for a charge pump circuit 失效
标题翻译：电荷泵电路的基本阶段
公开(公告)号：US07002399B2
公开(公告)日：2006-02-21
申请号：US10402852
申请日：2003-03-28
申请人： Giovanni Nuzzarello , Jacopo Mulatti
发明人： Giovanni Nuzzarello , Jacopo Mulatti
IPC分类号： G05F3/16
CPC分类号： H02M3/073 , G11C5/145 , H02M2003/071
摘要： A basic stage for a charge pump circuit having at least an input terminal and an output terminal and comprising: at least a first inverter inserted between said input and output terminals and comprising a first complementary pair of transistors, defining a first internal node, at least a second inverter inserted between said input and output terminals and comprising a second complementary pair of transistors, defining a second internal node, respective first and second capacitors connected to said first and second internal nodes and receiving first and second driving signals; the first and second pairs of transistors having the control terminals cross-connected to the second and first internal nodes. Advantageously, the basic stage comprises at least a first biasing structure connected to the first and second internal nodes and comprising first and second biasing transistors, which are respectively coupled to said first and second inverters.
摘要翻译：一种用于至少具有输入端子和输出端子的电荷泵电路的基本步骤，包括：至少插入在所述输入和输出端子之间的第一反相器，并且包括第一互补对晶体管，至少限定第一内部节点第二反相器插入在所述输入和输出端之间，并且包括限定第二内部节点的第二互补对晶体管，连接到所述第一和第二内部节点的相应的第一和第二电容器，以及接收第一和第二驱动信号; 所述第一和第二对晶体管具有与第二和第一内部节点交叉连接的控制端子。有利地，基本级包括连接到第一和第二内部节点的至少第一偏置结构，并且包括分别耦合到所述第一和第二逆变器的第一和第二偏置晶体管。

2. 发明授权

US07729177B2 Page buffer for nonvolatile memory device 有权
标题翻译：非易失性存储器件的页缓冲器
公开(公告)号：US07729177B2
公开(公告)日：2010-06-01
申请号：US11759649
申请日：2007-06-07
申请人： Dae Sik Song , Jaeseok Park , Jacopo Mulatti
发明人： Dae Sik Song , Jaeseok Park , Jacopo Mulatti
IPC分类号： G11C16/06 , G11C16/10 , G11C16/26 , G11C7/10 , G11C7/06
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/24 , G11C16/26 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643
摘要： A nonvolatile memory device implements a program routine followed by a program-verify routine when recording or modifying stored data. The nonvolatile memory device may include an array of memory cells for storing data, a sense node, and a gating circuit for selectively connecting a bitline of the array of memory cells to the sense node. The nonvolatile memory device may also include a page buffer coupled to the sense node. The page buffer may include a main latch for storing data to be written in the nonvolatile memory device, a cache latch for storing data supplied on an input line of the nonvolatile memory device to be transferred in the main latch through a source liner and a temporary static latch connected to the main latch through the source line and to the cache latch through an auxiliary switch and for transferring data between the main latch and the cache latch. The cache latch may be isolated from the source line during execution of the program routine and of the program-verify routine.
摘要翻译：非易失性存储器件在记录或修改存储的数据时实现程序例程，随后是程序验证程序。非易失性存储器件可以包括用于存储数据的存储器单元阵列，感测节点和用于选择性地将存储器单元阵列的位线连接到感测节点的选通电路。非易失性存储器件还可以包括耦合到感测节点的页缓冲器。页面缓冲器可以包括用于存储要写入非易失性存储器件的数据的主锁存器，用于存储提供在非易失性存储器件的输入线上的数据的高速缓冲存储器，用于通过源衬垫传输到主锁存器中，静态锁存器通过源极线连接到主锁存器，并通过辅助开关连接到高速缓存锁存器，并用于在主锁存器和高速缓存锁存器之间传送数据。在执行程序例程和程序验证程序期间，高速缓存锁存器可以与源线隔离。

3. 发明授权

US06898745B2 Integrated device with operativity testing 失效
标题翻译：具有可操作性测试的集成设备
公开(公告)号：US06898745B2
公开(公告)日：2005-05-24
申请号：US09798347
申请日：2001-03-02
申请人： Stefano Zanardi , Maurizio Branchetti , Jacopo Mulatti , Massimiliano Picca
发明人： Stefano Zanardi , Maurizio Branchetti , Jacopo Mulatti , Massimiliano Picca
IPC分类号： G01R31/317 , G11C29/46 , G01R31/28
CPC分类号： G11C29/46 , G01R31/31701
摘要： An integrated device having a pad receiving, in a standard operative condition, an input signal having a first value and, in a test operative condition, a test voltage having a second value higher than the first value; an input stage connected to the pad and including an electronic component having a first terminal connected to the pad; a third-level detecting stage connected to the pad and supplying a logic third-level signal having a first level in presence of the input signal and a second level in presence of the test voltage; and a selector connected to a second terminal of the electronic component and structured to connect the second terminal to a reference potential in the presence of the first logic level of the third-level signal and to a biasing voltage higher than the reference potential and lower than the second value in the presence of the second logic level of the third-level signal.
摘要翻译：一种集成装置，具有在标准操作条件下接收具有第一值的输入信号的焊盘，并且在测试操作条件下接收具有高于第一值的第二值的测试电压; 输入级，其连接到所述焊盘并且包括具有连接到所述焊盘的第一端子的电子部件; 连接到所述焊盘的第三电平检测级，并且在所述测试电压存在的情况下提供具有所述输入信号的第一电平的逻辑第三电平信号和第二电平; 以及选择器，其连接到所述电子部件的第二端子，并且被构造为在所述第三电平信号的所述第一逻辑电平存在的情况下将所述第二端子连接到参考电位，并且高于所述参考电位并且低于所述参考电位的偏置电压存在第三级信号的第二逻辑电平的第二值。

4. 发明授权

US06507183B1 Method and a device for measuring an analog voltage in a non-volatile memory 有权
标题翻译：用于测量非易失性存储器中的模拟电压的方法和装置
公开(公告)号：US06507183B1
公开(公告)日：2003-01-14
申请号：US09608847
申请日：2000-06-29
申请人： Jacopo Mulatti , Marco Maccarrone
发明人： Jacopo Mulatti , Marco Maccarrone
IPC分类号： G01R1706
CPC分类号： G11C29/02 , G11C16/04 , G11C16/30 , G11C29/50 , G11C2029/5004
摘要： Presented is an analog voltage value measuring device for measuring any of a set of voltage references that are generated inside a memory architecture. The selected voltage to be measured is connected to a facility line through a multiplexer. The memory architecture includes a set of output buffers connected to a respective set of output pads. The device also includes a converter block, connected between the facility line and the output buffers of the memory architecture for converting a measured analog value of a voltage reference selected by the multiplexer to a digital value, which is presented on the output pads. A method of measuring an analog voltage value in a memory device is also disclosed. The method includes selecting an analog voltage value from the set of voltage values; transferring the selected analog value onto the facility line; converting the selected analog value to a digital value; and presenting the digital value on the output pads.
摘要翻译：提出了一种模拟电压值测量装置，用于测量在存储器架构内产生的一组电压基准的任何一个。所选择的被测电压通过多路复用器连接到设备线。存储器架构包括连接到相应的一组输出焊盘的一组输出缓冲器。该设备还包括一个连接在设备线路和存储器结构的输出缓冲器之间的转换器模块，用于将由多路复用器选择的电压基准测量的模拟值转换成在输出焊盘上呈现的数字值。还公开了一种测量存储器件中的模拟电压值的方法。该方法包括从该组电压值中选择模拟电压值; 将所选择的模拟值传送到设备线上; 将所选择的模拟值转换为数字值; 并在输出板上显示数字值。

5. 发明授权

US06285614B1 Voltage regulator for single feed voltage memory circuits, and flash type memory in particular 有权
标题翻译：单馈电压存储电路的电压调节器，特别是闪存型存储器
公开(公告)号：US06285614B1
公开(公告)日：2001-09-04
申请号：US09602669
申请日：2000-06-26
申请人： Jacopo Mulatti , Marcello Carrera , Stefano Zanardi , Maurizio Branchetti
发明人： Jacopo Mulatti , Marcello Carrera , Stefano Zanardi , Maurizio Branchetti
IPC分类号： G11C702
CPC分类号： G11C5/147 , G11C16/30
摘要： A voltage regulator for memory circuits has a differential stage having a non-inverting input terminal receiving a control voltage independent of the temperature; an inverting input terminal connected to a ground voltage reference; a feed terminal connected to a booster circuit adapted for producing a boosted voltage; and an output terminal connected to an output terminal of the voltage regulator, for producing an output voltage reference starting from the comparison of input voltages. The voltage regulator further comprises a connecting transistor inserted between the feed terminal and the output terminal of the differential stage, the connecting transistor being source follower having a control terminal connected to the output terminal of the differential stage, as well as a source terminal connected to the output terminal of the voltage regulator, in such a way as to self-limit the transition of the voltage on the output terminal.
摘要翻译：用于存储器电路的电压调节器具有差分级，其具有接收与温度无关的控制电压的非反相输入端; 连接到接地电压基准的反相输入端子; 连接到适于产生升压电压的升压电路的馈电端子; 以及连接到所述电压调节器的输出端子的输出端子，用于从输入电压的比较开始产生输出电压基准。电压调节器还包括插入差分级的馈电端子和输出端子之间的连接晶体管，连接晶体管是源极跟随器，其具有连接到差分级的输出端子的控制端子，以及连接到电压调节器的输出端子，以自限制输出端子上的电压的转换。

6. 发明授权

US6075402A Positive charge pump 失效
标题翻译：正电荷泵
公开(公告)号：US6075402A
公开(公告)日：2000-06-13
申请号：US946727
申请日：1997-10-08
申请人： Andrea Ghilardelli , Jacopo Mulatti , Stefano Ghezzi
发明人： Andrea Ghilardelli , Jacopo Mulatti , Stefano Ghezzi
IPC分类号： H02M3/07 , G05F1/10
CPC分类号： H02M3/073
摘要： A charge pump comprises a plurality of stages connected in series, an input terminal of the charge pump being connected to a voltage supply and an output terminal of the charge pump providing an output voltage higher than the voltage supply. Each stage comprises unidirectional current flow MOS transistor means connected between a stage input terminal and a stage output terminal allowing current to flow only from said stage input terminal to said stage output terminal, and a first capacitor with one plate connected to said stage output terminal and another plate driven by a respective first digital signal periodically switching between ground and said voltage supply. The unidirectional current flow MOS transistor means of the stages have independent bulk electrodes, and a bias voltage generator circuit is provided for biasing the bulk electrodes of said unidirectional current flow MOS transistor means at respective bulk potentials which become progressively higher going from the stages proximate to said input terminal to the stages proximate to said output terminal of the charge pump.
摘要翻译：电荷泵包括串联连接的多个级，电荷泵的输入端连接到电压源，电荷泵的输出端提供高于电压源的输出电压。每个级包括连接在级输入端和级输出端之间的单向电流MOS晶体管装置，允许电流仅从所述级输入端流向所述级输出端;以及第一电容器，其一板连接到所述级输出端，以及由相应的第一数字信号驱动的另一个板，周期性地在接地和所述电压源之间切换。级的单向电流MOS晶体管装置具有独立的体电极，并且提供偏置电压发生器电路，用于以相应的体积电位偏压所述单向电流流量MOS晶体管装置的体电极，其逐渐地从接近于所述输入端子接近电荷泵的所述输出端子的级。

7. 发明授权

US06981107B2 Fast programming method for nonvolatile memories, in particular flash memories, and relative memory architecture 有权
标题翻译：用于非易失性存储器，特别是闪速存储器和相对存储器架构的快速编程方法
公开(公告)号：US06981107B2
公开(公告)日：2005-12-27
申请号：US10281078
申请日：2002-10-24
申请人： Guido Lomazzi , Jacopo Mulatti , St fano Surico
发明人： Guido Lomazzi , Jacopo Mulatti , St fano Surico
IPC分类号： G11C16/10 , C06F12/00
CPC分类号： G11C16/10 , G11C2216/14 , G11C2216/16
摘要： The programming method includes the following steps: sequentially receiving a plurality of data words; temporarily storing each data word after its reception; and simultaneously writing in parallel the plurality of stored data words in a memory array. After reception and temporary storage of each data word, the memory increments an address counter and sends a “ready” signal. Upon reception of each new data word, the memory verifies whether the address associated thereto is in the same sector as the initial data word and whether n data words have already been stored. If the sector is different, blind-programming step is terminated and the verifying is carried out; if the sector is the same but n data words have already been stored temporarily, the memory writes the temporarily stored words in the memory array, updates the address counter, and then sends the “ready” signal.
摘要翻译：编程方法包括以下步骤：顺序地接收多个数据字; 在接收后临时存储每个数据字; 并且同时将多个存储的数据字并行地写入存储器阵列中。在每个数据字的接收和临时存储之后，存储器增加一个地址计数器并发送一个“就绪”信号。在接收到每个新的数据字时，存储器验证与其相关联的地址是否在与初始数据字相同的扇区中，以及是否已经存储了n个数据字。如果扇区不同，则盲编程步骤终止并进行验证; 如果扇区是相同的，但是n个数据字已经被临时存储，则存储器将临时存储的字写入存储器阵列，更新地址计数器，然后发送“就绪”信号。

8. 发明授权

US06392936B1 Method and apparatus for generating from a single supply line voltages internal to a flash memory with reduced settling times 有权
标题翻译：用于从单个电源线产生闪存的内部电压降低的稳定时间的方法和装置
公开(公告)号：US06392936B1
公开(公告)日：2002-05-21
申请号：US09608239
申请日：2000-06-30
申请人： Jacopo Mulatti , Marco Maccarrone
发明人： Jacopo Mulatti , Marco Maccarrone
IPC分类号： G11C1300
CPC分类号： G11C5/147 , G11C16/12 , G11C16/30
摘要： Presented is a memory architecture including at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted references are in turn connected to first, second and third adjusters, which are adapted to provide respective first, second and third voltage references as required for the operations of programming, erasing and verifying cells of the memory architecture. At least a first switch block is used that connects between the first and third circuit nodes and is controlled by a first control signal to place the first and third high-voltage references in parallel during cell verify operations, thereby to provide one equivalent high-voltage source having a higher capacity for current than individual sources and effectively speed up the charging of the first circuit node so as to shorten the settling time of the first voltage reference. A method is also presented for generating voltage references with a reduced value of settling time as produced within a memory architecture.
摘要翻译：提出了一种存储器架构，其包括至少第一，第二和第三升压电路，其适于在相应的第一，第二和第三电路节点上产生至少第一，第二和第三升压电压基准。这些升压参考依次连接到第一，第二和第三调节器，其适于提供针对存储器结构的编程，擦除和验证单元的操作所需的相应的第一，第二和第三电压基准。至少使用连接在第一和第三电路节点之间的第一开关块，并且由第一控制信号控制，以在单元验证操作期间并行地布置第一和第三高压基准，从而提供一个等效的高电压源具有比单个源更高的电流容量，并且有效地加速第一电路节点的充电，以便缩短第一参考电压的建立时间。还提出了一种用于产生具有在存储器架构内产生的建立时间的降低的值的电压基准的方法。

9. 发明授权

US06266222B1 ESD protection network for circuit structures formed in a semiconductor 有权
标题翻译：用于在半导体中形成的电路结构的ESD保护网络
公开(公告)号：US06266222B1
公开(公告)日：2001-07-24
申请号：US09223621
申请日：1998-12-30
申请人： Paolo Colombo , Jacopo Mulatti , Roberto Annunziata , Giovanni Campardo , Marco Maccarrone
发明人： Paolo Colombo , Jacopo Mulatti , Roberto Annunziata , Giovanni Campardo , Marco Maccarrone
IPC分类号： H02H904
CPC分类号： H01L27/0259 , H01L27/0251
摘要： An ESD protection network protects a CMOS circuit structure integrated in a semiconductor substrate. The circuit structure includes discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply having a respective primary ground, and from at least one secondary voltage supply having a respective secondary ground. This network includes a first ESD protection element for an input stage of the circuit structure; a second ESD protection element for an output stage of the circuit structure, the first and second protection elements having an input/output pad of the integrated circuit structure in common; a first ESD protection element between the primary supply and the primary ground; and a second ESD protection element between the secondary supply and the secondary ground.
摘要翻译： ESD保护网络保护集成在半导体衬底中的CMOS电路结构。电路结构包括形成在相应的衬底部分中的分立电路块，它们彼此电绝缘并且由至少一个具有各自的初级接地的初级电压源以及至少一个具有相应次级接地的次级电压源独立供电。该网络包括用于电路结构的输入级的第一ESD保护元件; 用于所述电路结构的输出级的第二ESD保护元件，所述第一和第二保护元件具有所述集成电路结构的输入/输出焊盘; 主要供电和主地面之间的第一个ESD保护元件; 以及在次级电源和次级接地之间的第二ESD保护元件。

10. 发明授权

US06184741B2 Bidirectional charge pump generating either a positive or negative voltage 失效
标题翻译：双向电荷泵产生正或负电压
公开(公告)号：US06184741B2
公开(公告)日：2001-02-06
申请号：US08900165
申请日：1997-07-28
申请人： Andrea Ghilardelli , Giovanni Campardo , Jacopo Mulatti
发明人： Andrea Ghilardelli , Giovanni Campardo , Jacopo Mulatti
IPC分类号： G05F110
CPC分类号： G11C5/145
摘要： A charge pump comprises at least one charge pump stage including a first diode having an anode and a cathode, and a capacitor having a first plate connected to the cathode of the diode and a second plate connected to a clock signal that periodically varies between a reference voltage and a supply voltage, the anode of said diode forming a first terminal of the charge pump. The charge pump further comprises a second diode having an anode connected to the cathode of the first diode and a cathode forming a second terminal of the charge pump, first switching means for selectively coupling the first terminal of the charge pump to the voltage supply and second switching means for selectively coupling the second terminal of the charge pump to the reference voltage. The first switching means and the second switching means are respectively closed and open in a first operating condition whereby the second terminal of the charge pump acquires a voltage of the same polarity but higher in absolute value than said supply voltage. The first switching means and the second switching means are respectively open and closed in a second operating condition whereby the first terminal of the charge pump acquires a voltage of opposite polarity with respect to said voltage supply.
摘要翻译：电荷泵包括至少一个电荷泵级，其包括具有阳极和阴极的第一二极管，以及具有连接到二极管的阴极的第一板的电容器和连接到时钟信号的第二板，所述时钟信号周期性地在参考电压和电源电压，所述二极管的阳极形成电荷泵的第一端子。电荷泵还包括具有连接到第一二极管的阴极的阳极和形成电荷泵的第二端子的阴极的第二二极管，用于选择性地将电荷泵的第一端子耦合到电压源的第一开关装置和第二二极管用于选择性地将电荷泵的第二端子耦合到参考电压的开关装置。第一开关装置和第二开关装置分别在第一操作条件下闭合和断开，由此电荷泵的第二端子获得与所述电源电压相同的极性但绝对值高的电压。第一开关装置和第二开关装置分别在第二操作条件下打开和关闭，由此电荷泵的第一端子获得相对于所述电压源的极性相反的电压。

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