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1. 发明授权

US6069513A Toggle flip-flop network with a reduced integration area 失效
标题翻译：切换触发器网络，减少集成区域
公开(公告)号：US6069513A
公开(公告)日：2000-05-30
申请号：US141709
申请日：1998-08-28
申请人： Annamaria Rossi , Giona Fucili , Marcello Leone , Maurizio Nessi
发明人： Annamaria Rossi , Giona Fucili , Marcello Leone , Maurizio Nessi
IPC分类号： H03K3/037 , H03K3/356
CPC分类号： H03K3/037 , H03K3/356113
摘要： A toggle flip-flop with reduced integration area, comprising a flip-flop of the D-type with an inverting input stage and a master-slave portion. Three transistors connected to the inverting stage form a logic gate of the XOR type whereto the output terminal of the master-slave portion is fed back.
摘要翻译：具有减小的积分区域的切换触发器，包括具有反相输入级的D型触发器和主从部分。连接到反相级的三个晶体管形成XOR类型的逻辑门，其中主从部分的输出端被反馈。

2. 发明授权

US5886484A Masking of switching noise in controlling a "H" bridge 失效
标题翻译：在控制“H”桥时屏蔽开关噪声
公开(公告)号：US5886484A
公开(公告)日：1999-03-23
申请号：US650531
申请日：1996-05-20
申请人： Giona Fucili , Maurizio Nessi
发明人： Giona Fucili , Maurizio Nessi
IPC分类号： H02P7/03 , H02K23/00
CPC分类号： H02P7/04
摘要： Masking of switching noise is implemented in the driving system of an "H" bridge stage by exploiting the periodic signal generated by a PWM control circuit (normally present in the control system for controlling the "H" bridge in an open-loop mode) for masking the decay time of the disturbances caused by the switching from off-to-on of a first pair of switches of the bridge that drive a current in a certain direction through the load. This is implemented by keeping high for a preset period of time the periodic signal generated by the PWM circuit and varying the duty-cycle of the signal for regulating the mask time in function of the load characteristics. The system further comprises the masking of the decay interval of the disturbances caused by the switching from on-to-off of the first pair of switches and from off-to-on of the other pair of switches that provides a current ricirculation path of the energy stored in the reactance of the load, for a preset number of clock cycles, thus impeding any subsequent switching for the duration of this second mask. This second mask may be realized in different ways. The use of an up-counter and a programmable comparator is preferred.
摘要翻译：通过利用由PWM控制电路产生的周期性信号（通常存在于用于控制开环模式中的“H”桥）的控制系统中），在“H”桥级的驱动系统中实现开关噪声的屏蔽，用于掩蔽由桥接器的第一对开关的切换到由特定方向驱动电流通过负载而导致的干扰的衰减时间。这是通过在PWM电路产生的周期信号的预设时间段内保持高电平并且根据负载特性改变用于调节掩模时间的信号的占空比来实现的。该系统还包括屏蔽由第一对开关的开关断开引起的干扰的衰减间隔，以及提供另一对开关的另一对开关的衰减间隔的屏蔽，该开关提供当前的存储在负载的电抗中的能量达预设数量的时钟周期，从而阻止在该第二掩模的持续时间内的任何后续切换。该第二掩模可以以不同的方式实现。优选使用递增计数器和可编程比较器。

3. 发明授权

US5469096A Power-transistor slew-rate controller employing only a single capacitor per half-bridge 失效
标题翻译：功率晶体管转换速率控制器，每半桥采用单个电容
公开(公告)号：US5469096A
公开(公告)日：1995-11-21
申请号：US251693
申请日：1994-05-31
申请人： Maurizio Nessi , Giona Fucili
发明人： Maurizio Nessi , Giona Fucili
IPC分类号： H02P6/10 , H02P6/08 , H03K3/00
CPC分类号： H02P6/085
摘要： In a half-bridge output stage employing a complementary pair of output power transistors, each driven through an integrating stage for controlling the slew-rate, a single integration capacitance is conveniently shared by the two integrating stages that drive the power transistors. A pair of switches connect the single integrating capacitance to the input of either one of the two integrating stages and are controlled by a pair of nonoverlapping signals that have a certain advance with respect to the pair of logic signals that drive the half-bridge stage. In the case of a driving system of a multi-phase machine, the two configuring switches of the single integration capacitor may be driven by a pair of control signals that drive a different phase winding of the multi-phase machine, thus eliminating the need for dedicated circuitry for generating said pair of anticipated signals to control the configuration switches.
摘要翻译：在采用互补输出功率晶体管对的半桥输出级中，每个驱动通过用于控制转换速率的积分级，由驱动功率晶体管的两个积分级方便地共享单个积分电容。一对开关将单个积分电容连接到两个积分级中的任一个的输入，并且由一对非重叠信号控制，该对重叠信号相对于驱动半桥级的逻辑信号对具有一定的提前。在多相机的驱动系统的情况下，单一积分电容器的两个配置开关可以由驱动多相机的不同相绕组的一对控制信号驱动，因此不需要用于产生所述一对预期信号以控制配置开关的专用电路。

4. 发明授权

US06154163A Successive approximation shift register with reduced latency 失效
标题翻译：逐次逼近移位寄存器，降低延迟
公开(公告)号：US06154163A
公开(公告)日：2000-11-28
申请号：US108080
申请日：1998-06-29
申请人： Annamaria Rossi , Giona Fucili , Marcello Leone , Maurizio Nessi
发明人： Annamaria Rossi , Giona Fucili , Marcello Leone , Maurizio Nessi
IPC分类号： H03M1/46 , H03M1/38
CPC分类号： H03M1/462
摘要： A successive approximation register has a serial input and output comprises a chain of logic circuits of the bistable type which have selectable input terminals feedback connected by a storage and control element and logic gate circuits of the OR-type, and connected to a serial line through respective internal switches communicating the serial line to input terminals of the logic circuits in said chain, the serial line forming an input to a flip-flop of the D type which is the output element of the register.
摘要翻译：逐次逼近寄存器具有串行输入和输出，其包括双稳态类型的逻辑电路链，其具有通过存储和控制元件反馈连接的可选输入端和OR型逻辑门电路，并连接到串行线各个内部开关将串行线路传送到所述链路中的逻辑电路的输入端，该串行线路形成作为寄存器的输出元件的D型触发器的输入。

5. 发明授权

US5943000A Compensated MOS string and DAC employing such a potentiometric string 失效
标题翻译：补偿MOS串和DAC采用这样的电位串
公开(公告)号：US5943000A
公开(公告)日：1999-08-24
申请号：US956273
申请日：1997-10-22
申请人： Maurizio Nessi , Rinaldo Castello , Giona Fucili , Marcello Leone , Annamaria Rossi
发明人： Maurizio Nessi , Rinaldo Castello , Giona Fucili , Marcello Leone , Annamaria Rossi
IPC分类号： H03M1/06 , H03M1/68 , H03M1/76 , H03M1/78
CPC分类号： H03M1/682 , H03M1/0602 , H03M1/765
摘要： A digital-to-analog converter includes a potentiometric string suitable for realizing a relatively high number of bits that significantly reduces the silicon area requirement and simplifies mismatch compensation. The structure includes a first resistance string to realize a first DAC to convert a first number of most significative bits, and a second potentiometric string functionally connected in cascade to the first, but realized with MOS transistors. The structure of the invention allows the coupling of the two DACs in cascade by exploiting the MOS transistors that form the second potentiometric string, that is, the second DAC, thus avoiding the use of operational switches or amplifiers which may provide error sources. Moreover, the structure of the invention lends itself to the implementation of efficient compensation circuits for integral and differential linearity errors.
摘要翻译：数模转换器包括适于实现相对较高数量的位的电位串，其显着地降低了硅面积需求并简化了不匹配补偿。该结构包括第一电阻串，以实现第一DAC以转换第一数量最有意义的位，以及第二电位串，其功能上串联连接到第一电位，但是用MOS晶体管实现。本发明的结构允许通过利用形成第二电位串的MOS晶体管（即第二DAC）级联耦合两个DAC，从而避免使用可能提供误差源的操作开关或放大器。此外，本发明的结构适用于实现用于积分和微分线性误差的有效补偿电路。

6. 发明授权

US5422923A Programmable time-interval generator 失效
标题翻译：可编程时间间隔发生器
公开(公告)号：US5422923A
公开(公告)日：1995-06-06
申请号：US222253
申请日：1994-03-31
申请人： Giona Fucili , Maurizio Nessi
发明人： Giona Fucili , Maurizio Nessi
IPC分类号： G04F5/00 , G06F1/025 , G06F7/62 , H02P6/08 , H03K5/13 , H03K21/38 , H03K21/00
CPC分类号： H03K5/13 , G06F1/025 , G06F7/62
摘要： A programmable time-intervals generator comprising first and second digital counters, a memory, a digital divider and a digital adder. On the occurrence of a first event, the first counter starts counting, and on the occurrence of a second event, only the most significant bits of the number counted up to then are stored, thereby providing a division by truncation. From the stored number, at least two discrete fractions are obtained by the divider, whereafter said fractions are summed at the adder which operates on strings of bits. The second counter counts down the sum number and, on becoming cleared, generates a signal.
摘要翻译：一种可编程时间间隔发生器，包括第一和第二数字计数器，存储器，数字除法器和数字加法器。在发生第一事件时，第一个计数器开始计数，并且在第二个事件发生时，仅存储直到此数的最高有效位，从而通过截断进行除法。从存储的数字中，通过除法器获得至少两个离散分数，之后所述分数在加法器处相加，该加法器对位串进行操作。第二个计数器对和号进行计数，并在清零时产生一个信号。

7. 发明授权

US06249099B1 Silent phase commutation in a three-phase brushless DC motor 有权
标题翻译：三相无刷直流电机静音相位换向
公开(公告)号：US06249099B1
公开(公告)日：2001-06-19
申请号：US09345694
申请日：1999-06-30
申请人： Maurizio Nessi , Ezio Galbiati , Pierandrea Savo , Giorgio Sciacca , Luca Schillaci
发明人： Maurizio Nessi , Ezio Galbiati , Pierandrea Savo , Giorgio Sciacca , Luca Schillaci
IPC分类号： H02P750
CPC分类号： H02P6/10
摘要： A method drives a three-phase motor having first, second, and third coils. The method electrically connects the first coil to a first voltage reference and the second coil to a second voltage reference while leaving the other coil floating during a first driving phase. During a second driving phase, the first coil is electrically connected to the first voltage reference and the third coil is electrically connected to the second voltage reference while the second coil is left floating. During a transition phase that immediately follows the fast driving phase and immediately precedes the second driving phase, the second coil is electrically connected alternately to the first and second voltage references. By alternately connecting the second coil to the first second voltage references and during the transition phase, the method causes the current through the second coil to reduce to zero at a slower rate than prior methods. This enables the variations of the currents that the two phases in commutation, the second and third coils, to happen in a way that maintains their sum constant, as much as possible. This reduces the torque ripple during the phase commutations and its accompanying acoustic noise.
摘要翻译：一种驱动具有第一，第二和第三线圈的三相电动机的方法。该方法在第一驱动阶段期间将第一线圈电连接到第一参考电压并将第二线圈电连接到第二参考电压，同时使另一线圈浮置。在第二驱动阶段期间，第一线圈电连接到第一参考电压，而第三线圈电连接到第二参考电压，而第二线圈悬空。在紧接着快速驱动相位并且紧接在第二驱动相位之前的转变阶段期间，第二线圈交替地电连接到第一和第二参考电压。通过交替地将第二线圈连接到第一第二电压基准，并且在转变阶段期间，该方法使得通过第二线圈的电流以比现有方法更慢的速率减小到零。这使得能够以尽可能多的方式使换相，第二和第三线圈中的两相的电流的变化以保持它们的和恒定的方式发生。这降低了相位转换期间的转矩脉动及其伴随的声学噪声。

8. 发明授权

US06727838B2 Tracking analog-to-digital converter 有权
标题翻译：跟踪模数转换器
公开(公告)号：US06727838B2
公开(公告)日：2004-04-27
申请号：US10254371
申请日：2002-09-25
申请人： Luca Schillaci , Alessandro Scrivani , Simone Silvestri , Maurizio Nessi
发明人： Luca Schillaci , Alessandro Scrivani , Simone Silvestri , Maurizio Nessi
IPC分类号： H03M134
CPC分类号： H03M1/48
摘要： The present invention herein describes a tracking analog-to-digital converter, in particular of the differential input type. In an embodiment thereof the tracking analog-to-digital converter, having a differential analog input including a first analog input and a second analog input, and a digital output at a first number of bits comprising: a back and forth counter having a direction input and an output, with a second number of bits; a digital-to-analog converter having a data input coupled to said output of said converter, a reference input and an output, with a second number of bits; a first comparator having a positive input, a negative input coupled to said output of said digital-to-analog converter and an output coupled to said direction input; characterized in that said reference input is coupled to said first analog input and said positive input of said first comparator is coupled to said second analog input.
摘要翻译：本发明在此描述了特别是差分输入类型的跟踪模数转换器。在其实施例中，跟踪模数转换器具有包括第一模拟输入和第二模拟输入的差分模拟输入以及以第一位数的数字输出，包括：带有第二位数的具有方向输入和输出的前后计数器; 具有耦合到所述转换器的所述输出的数据输入的数/模转换器，具有第二位数的参考输入和输出; 具有正输入的第一比较器，耦合到所述数模转换器的所述输出的负输入和耦合到所述方向输入的输出; 其特征在于，所述参考输入耦合到所述第一模拟输入，所述第一比较器的所述正输入端耦合到所述第二模拟输入。

9. 发明授权

US06417639B1 Control circuit for a hard disk drive head 有权
标题翻译：硬盘驱动器头的控制电路
公开(公告)号：US06417639B1
公开(公告)日：2002-07-09
申请号：US09564307
申请日：2000-05-03
申请人： Luca Schillaci , Maurizio Nessi , Giorgio Sciacca
发明人： Luca Schillaci , Maurizio Nessi , Giorgio Sciacca
IPC分类号： G05B1101
CPC分类号： G11B5/59605 , G11B5/5526
摘要： A positioning system for a read/write head of a disk drive includes a rotatable data disk, a read/write head movable over the disk, a voice coil motor (VCM) connected to the head and a source of digital position signals. A control circuit includes means for generating a VCM control current, a sensor for sensing the VCM current and an amplifier having an inverting input connected to a reference voltage source through a resistor and to a sensor output, a non-inverting input connected to the source of digital position signals through a DAC and an output connected to an input of the drive means.
摘要翻译：用于磁盘驱动器的读/写头的定位系统包括可旋转数据盘，可移动到盘上的读/写头，连接到头的音圈电机（VCM）和数字位置信号源。控制电路包括用于产生VCM控制电流的装置，用于感测VCM电流的传感器和具有通过电阻器连接到参考电压源的反相输入和传感器输出的放大器，连接到源的非反相输入的数字位置信号通过DAC和连接到驱动装置的输入的输出。

10. 发明授权

US6094022A Low jitter zero crossing BEMF detector and motor incorporating the same 有权
标题翻译：低抖动零交叉BEMF检测器和并入其的电动机
公开(公告)号：US6094022A
公开(公告)日：2000-07-25
申请号：US346650
申请日：1999-07-01
申请人： Luca Schillaci , Maurizio Nessi , Giacomino Bollati , Ezio Galbiati
发明人： Luca Schillaci , Maurizio Nessi , Giacomino Bollati , Ezio Galbiati
IPC分类号： H02P6/18 , H02K23/00
CPC分类号： H02P6/182
摘要： A BEMF detector and method detect the BEMF of a three-phase motor using a fully differential detection system. The motor has a first coil coupled between a first coil tap and a center tap, a second coil coupled between a second coil tap and the center tap, and a third coil coupled between a third coil tap and the center tap. The BEMF detector includes a differential amplifier having first and second inputs and first and second outputs, with the first input being coupled to one of the coil taps and the second input being coupled to the center tap. The BEMF detector also includes a comparator having first and second inputs coupled respectively to the first and second outputs of the differential amplifier and an output at which a BEMF signal is produced that is related to the BEMF of the motor. The differential amplifier may be part of an anti-alias filter structured to fix to a known stable value a common mode at the outputs of the differential amplifier. The BEMF detector also may include one or more fully differential filters positioned between the differential amplifier and the comparator to reduce noise and smooth the BEMF signal output by the comparator. One of the filters can be a linear phase, switched capacitor filter with a stable cutoff frequency.
摘要翻译： BEMF检测器和方法使用完全差分检测系统检测三相电机的BEMF。电动机具有耦合在第一线圈抽头和中心抽头之间的第一线圈，耦合在第二线圈抽头和中心抽头之间的第二线圈以及耦合在第三线圈抽头和中心抽头之间的第三线圈。 BEMF检测器包括具有第一和第二输入以及第一和第二输出的差分放大器，其中第一输入耦合到线圈抽头之一并且第二输入耦合到中心抽头。 BEMF检测器还包括比较器，其具有分别耦合到差分放大器的第一和第二输出端的第一和第二输入端以及产生与马达的BEMF有关的BEMF信号的输出端。差分放大器可以是抗差分滤波器的一部分，其被构造为在差分放大器的输出处固定到已知稳定值的共模。 BEMF检测器还可以包括位于差分放大器和比较器之间的一个或多个全差分滤波器，以降低噪声并平滑比较器输出的BEMF信号。其中一个滤波器可以是具有稳定截止频率的线性相位开关电容滤波器。

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