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1. 发明授权

US06704555B2 Apparatus and method for calibrating local oscillation frequency in wireless communications 有权
标题翻译：无线通信校准本地振荡频率的装置和方法
公开(公告)号：US06704555B2
公开(公告)日：2004-03-09
申请号：US09804707
申请日：2001-03-12
申请人： Gilbert C. Sih , Raghu Challa
发明人： Gilbert C. Sih , Raghu Challa
IPC分类号： H04B106
CPC分类号： H04L27/0014 , H04L2027/0016 , H04L2027/0057 , H04L2027/0087
摘要： According to a disclosed embodiment, a receiver comprising a digital rotator in combination with a frequency error discriminator in a digital automatic frequency control loop is used to arrive at accurate digital values used to calibrate a local oscillation frequency. A frequency error in the oscillation frequency of a local frequency generation loop causes a change in the baseband input signal frequency. The change in the baseband input signal frequency related to the frequency error in the local frequency generation loop can be detected as a phase rotation by the frequency error discriminator. By using the digital automatic frequency control loop, the frequency error introduced by the local frequency generation is determined with accuracy. The frequency error and corresponding control bits are entered into a calibration table. The calibration table may be used to adjust the local oscillation frequency for temperature changes, pilot frequency searching, and quick paging.
摘要翻译：根据所公开的实施例，使用包括与数字自动频率控制环路中的频率误差鉴别器结合的数字旋转器的接收器来获得用于校准本地振荡频率的精确数字值。本地频率产生环路的振荡频率的频率误差导致基带输入信号频率的变化。与本地频率产生回路中的频率误差相关的基带输入信号频率的变化可以被频率误差鉴别器检测为相位旋转。通过使用数字自动频率控制回路，准确地确定由本地频率产生引入的频率误差。将频率误差和相应的控制位输入校准表。校准表可用于调整温度变化，导频搜索和快速寻呼的本地振荡频率。

2. 发明授权

US06608858B1 Multipath doppler adjusted frequency tracking loop 有权
标题翻译：多径多普勒调整频率跟踪回路
公开(公告)号：US06608858B1
公开(公告)日：2003-08-19
申请号：US09491349
申请日：2000-01-26
申请人： Gilbert C. Sih , Avneesh Agrawal , Mark Roh , Brian K. Butler , Raghu Challa
发明人： Gilbert C. Sih , Avneesh Agrawal , Mark Roh , Brian K. Butler , Raghu Challa
IPC分类号： H04B1707
CPC分类号： H04B1/7087 , H04B1/7115 , H04B1/7117 , H04B2201/70701 , H04L27/0014 , H04L2027/0032 , H04L2027/0057 , H04L2027/0087
摘要： A method and apparatus for frequency tracking is described. The present invention provides a tracking mechanism for removing the effects of error due to frequency offset as well as compensation for frequency error due to doppler in a plurality of multipath signals. Each finger of a RAKE receiver utilizing the present invention will compute a frequency error for that finger. The weighted average of all of these frequency errors is calculated and filtered to provide a control signal for varying the frequency of IF and RF frequency synthesizers, accounting for the common frequency offset seen at each finger. Additionally, each finger is equipped with a rotator for providing frequency adjustment specific to that finger. The frequency of each finger is adjusted through feedback of the frequency error for that finger.
摘要翻译：描述了用于频率跟踪的方法和装置。本发明提供了一种用于消除由于频率偏移引起的误差的影响的跟踪机制以及由多个多径信号中的多普勒引起的频率误差的补偿。利用本发明的RAKE接收机的每个手指将计算该手指的频率误差。计算并滤波所有这些频率误差的加权平均值，以提供用于改变IF和RF频率合成器的频率的控制信号，从而考虑每个手指处的共同频率偏移。此外，每个手指配备有用于提供特定于该手指的频率调节的旋转器。每个手指的频率通过该手指的频率误差的反馈进行调整。

3. 发明授权

US08665996B2 Efficient parallel sub-packet decoding using multiple decoders 有权
标题翻译：使用多个解码器的高效并行子包解码
公开(公告)号：US08665996B2
公开(公告)日：2014-03-04
申请号：US12400124
申请日：2009-03-09
申请人： Joseph Zanotelli , Mrinal Mahesh Nath , Arunava Chaudhuri , Kaushik Ghosh , Raghu Challa , Weihong Jing
发明人： Joseph Zanotelli , Mrinal Mahesh Nath , Arunava Chaudhuri , Kaushik Ghosh , Raghu Challa , Weihong Jing
IPC分类号： H04L27/06
CPC分类号： H04L1/0045 , H03M13/2957 , H03M13/41 , H03M13/6508 , H03M13/6561 , H04L1/0052
摘要： A configurable decoder within a receiver (for example, within a wireless communication device) includes numerous decoders. In one mode, the multiple decoders are used to decode different sub-packets of a packet. When one decoder completes decoding the last sub-packet assigned to it of the packet, then that decoder generates a packet done indication. A control circuit receives the packet done indications, and when all the decoders have generated packet done indications then the control circuit initiates an action. In one example, the action is the interrupting of a processor. The processor responds by reading status information from the control circuit, thereby resetting the interrupt. End-of-packet markers are usable to generate packet done indications and to generate EOP interrupts. Similarly, end-of-group markers are usable to generate group done indications and to generate EOG interrupts. The decoder block is configurable to process sub-packets of a packet using either one or multiple decoders.
摘要翻译：接收机内的可配置解码器（例如，在无线通信设备内）包括许多解码器。在一种模式中，多个解码器用于解码分组的不同子分组。当一个解码器完成对分组给它的最后一个子分组的解码时，该解码器产生分组完成指示。控制电路接收分组完成指示，并且当所有解码器已经生成分组完成指示时，控制电路启动动作。在一个示例中，动作是处理器的中断。处理器通过从控制电路读取状态信息进行响应，从而复位中断。分组结束标记可用于生成分组完成指示并产生EOP中断。类似地，组尾标记可用于生成组完成指示并产生EOG中断。解码器块可配置为使用一个或多个解码器来处理分组的子分组。

4. 发明授权

US08626099B2 Direct conversion receiver architecture 有权
标题翻译：直接转换接收机架构
公开(公告)号：US08626099B2
公开(公告)日：2014-01-07
申请号：US11376502
申请日：2006-03-14
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B1/06
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

5. 发明授权

US08615212B2 Direct conversion receiver architecture 有权
公开(公告)号：US08615212B2
公开(公告)日：2013-12-24
申请号：US11862330
申请日：2007-09-27
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B7/00
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

6. 发明授权

US07436412B2 Graphics engine with efficient interpolation 有权
标题翻译：具有高效插值的图形引擎
公开(公告)号：US07436412B2
公开(公告)日：2008-10-14
申请号：US11211939
申请日：2005-08-24
申请人： Raghu Challa
发明人： Raghu Challa
IPC分类号： G09G5/00 , G09G5/02 , G06K9/32 , G06T11/40
CPC分类号： G06T11/40 , G06T9/00 , G06T15/005 , G06T15/80
摘要： A graphics engine includes a setup unit and a rendering unit. The setup unit computes coefficients A, B, and C used for interpolating an attribute v of a triangle to be rendered for a graphics image. The setup unit then derives compressed coefficients Ã, {tilde over (B)}, and {tilde over (C)} based on the coefficients A, B, and C. The compressed coefficients have a fixed-point format with R integer bits left of a binary point and T fractional bits right of the binary point, where R>1 and T≧0. R is selected based on the number of bits used for attribute v, T is selected based on the screen dimension, and R+T is much less than the number of bits used to represent the coefficients A, B, and C. The rendering unit performs interpolation for the attribute v using the compressed coefficients Ã, {tilde over (B)}, and {tilde over (C)}, and may be implemented with a simple (R+T)-bit non-saturating accumulator.
摘要翻译：图形引擎包括设置单元和渲染单元。设置单元计算用于内插用于图形图像呈现的三角形的属性v的系数A，B和C. 设置单元然后基于系数A，B和C导出压缩系数∈B和C。压缩系数具有固定点格式，其中R个整数位为二进制点，T分数位为二进制位点，其中R> 1和T> = 0。基于用于属性v的位数选择R，基于屏幕尺寸选择T，并且R + T远小于用于表示系数A，B和C的比特数。渲染单元使用压缩系数∈B和C对属性v执行内插，并且可以用简单（R + T）位非饱和累加器来实现。

7. 发明授权

US06580746B2 System and method for acquiring a received signal in a spread spectrum device 有权
公开(公告)号：US06580746B2
公开(公告)日：2003-06-17
申请号：US09941362
申请日：2001-08-28
申请人： Raghu Challa , Farrokh Abrishamkar , Ian Fevrier , Serguei Glazko , Way-Shing Lee , Christopher Patrick , Gil Sih
发明人： Raghu Challa , Farrokh Abrishamkar , Ian Fevrier , Serguei Glazko , Way-Shing Lee , Christopher Patrick , Gil Sih
IPC分类号： H04B1500
CPC分类号： H04B1/7075 , H04B7/2668 , H04B17/0085 , H04B17/3912 , H04W24/00
摘要： A spread spectrum wireless device (100) may include a receiver (110), a searcher (128), a search controller (130) and other features. The search controller (130) selectively generates control signals to control the searcher (128), which searches for a spread-spectrum signal. In one embodiment, the architecture of the searcher (128) is dynamically configurable by the search controller (130) to selectively search multiple channels using multiple frequency bins for the signal.

8. 发明授权

US08520571B2 Reconfigurable wireless modem sub-circuits to implement multiple air interface standards 有权
标题翻译：可重配置的无线调制解调器子电路实现多个空中接口标准
公开(公告)号：US08520571B2
公开(公告)日：2013-08-27
申请号：US12396270
申请日：2009-03-02
申请人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Ali RostamPisheh , Raghu Challa , Hemanth Sampath , Megan Wu , Joseph Zanotelli , Mrinal Nath
发明人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Ali RostamPisheh , Raghu Challa , Hemanth Sampath , Megan Wu , Joseph Zanotelli , Mrinal Nath
IPC分类号： H04B7/00
CPC分类号： G06F15/7842
摘要： A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.
摘要翻译：灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。子电路的任务管理器可以配置和控制子电路的可配置硬件。中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。每个任务列表包括相应子电路的任务指令。子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

9. 发明授权

US08379778B2 Bursty interference suppression for communications receivers 有权
标题翻译：通信接收机的干扰抑制
公开(公告)号：US08379778B2
公开(公告)日：2013-02-19
申请号：US11875588
申请日：2007-10-19
申请人： Ming Yan , Raghu Challa
发明人： Ming Yan , Raghu Challa
IPC分类号： H03D1/04
CPC分类号： H04L25/03006 , H04L25/03178 , H04L2025/03407 , H04L2025/0377
摘要： Techniques are provided for suppressing interference by taking into account the possible bursty nature of co-channel interference in a communication system. In an aspect, interference levels are separately computed for first and second data portions of a desired signal. The computed interference levels may be used to scale the corresponding data portions for subsequent processing.
摘要翻译：提供了通过考虑通信系统中同信道干扰的可能突发性质来抑制干扰的技术。在一个方面，对期望信号的第一和第二数据部分分别计算干扰电平。所计算的干扰电平可用于缩放相应的数据部分用于后续处理。

10. 发明授权

US07801248B2 Interference suppression with virtual antennas 有权
标题翻译：虚拟天线的干扰抑制
公开(公告)号：US07801248B2
公开(公告)日：2010-09-21
申请号：US11122654
申请日：2005-05-04
申请人： Raghu Challa , Roland Reinhard Rick
发明人： Raghu Challa , Roland Reinhard Rick
IPC分类号： H04L27/06 , H03D1/04
CPC分类号： H04L25/03006 , H04L25/0328
摘要： A receiver suppresses co-channel interference (CCI) from other transmitters and intersymbol interference (ISI) due to channel distortion using “virtual” antennas. The virtual antennas may be formed by (1) oversampling a received signal for each actual antenna at the receiver and/or (1) decomposing a sequence of complex-valued samples into a sequence of inphase samples and a sequence of quadrature samples. In one design, the receiver includes a pre-processor, an interference suppressor, and an equalizer. The pre-processor processes received samples for at least one actual antenna and generates at least two sequences of input samples for each actual antenna. The interference suppressor suppresses co-channel interference in the input sample sequences and provides at least one sequence of CCI-suppressed samples. The equalizer performs detection on the CCI-suppressed sample sequence(s) and provides detected bits. The interference suppressor and equalizer may be operated for one or multiple iterations.
摘要翻译：由于使用“虚拟”天线的信道失真，接收机抑制来自其他发射机的同信道干扰（CCI）和码间干扰（ISI）。虚拟天线可以通过以下方式形成：（1）在接收机处对每个实际天线的接收信号进行过采样和/或（1）将复值样本序列分解为同相采样序列和正交采样序列。在一种设计中，接收机包括预处理器，干扰抑制器和均衡器。预处理器处理接收到的至少一个实际天线的样本，并为每个实际天线生成至少两个输入采样序列。干扰抑制器抑制输入样本序列中的同信道干扰，并提供至少一个CCI抑制样本序列。均衡器对CCI抑制的采样序列执行检测，并提供检测到的位。干扰抑制器和均衡器可以被操作一次或多次迭代。

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