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1. 发明授权

US07290228B2 Hardware accelerator with a single partition for latches and combinational logic 失效
标题翻译：具有单个分区的硬件加速器，用于锁存器和组合逻辑
公开(公告)号：US07290228B2
公开(公告)日：2007-10-30
申请号：US11064727
申请日：2005-02-24
申请人： Gernot E. Guenther , Viktor Gyuris , Harrell Hoffman , Kevin Anthony Pasnik , John Henry Westermann, Jr.
发明人： Gernot E. Guenther , Viktor Gyuris , Harrell Hoffman , Kevin Anthony Pasnik , John Henry Westermann, Jr.
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.
摘要翻译：硬件加速器包括仅组合的周期的硬件支持，并且锁存器仅在具有锁存器和组合逻辑的单个分区的仿真模型中循环。优选实施例在硬件加速器中使用特殊的4输入1输出功能单元来代替正常的锁存功能，该功能将仅存储组合的周期的旧锁存值回写。其他实施例包括针对阵列和透明锁存器的单独阵列写禁止的硬件支持，取决于该周期是仅组合周期和仅锁存周期。还包括依赖于硬件断点的发生的条件阵列写禁用，其支持从锁存器加组合周期切换到仅锁存周期，以在对锁存器发生断点时评估组合逻辑之前给予用户控制。

2. 发明授权

US07769577B2 Hardware accelerator with a single partition for latches and combinational logic 失效
标题翻译：具有单个分区的硬件加速器，用于锁存器和组合逻辑
公开(公告)号：US07769577B2
公开(公告)日：2010-08-03
申请号：US11848489
申请日：2007-08-31
申请人： Gernot E. Guenther , Viktor Gyuris , Harrell Hoffman , Kevin Anthony Pasnik , John Henry Westerman, Jr.
发明人： Gernot E. Guenther , Viktor Gyuris , Harrell Hoffman , Kevin Anthony Pasnik , John Henry Westerman, Jr.
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.
摘要翻译：硬件加速器包括仅组合的周期的硬件支持，并且锁存器仅在具有锁存器和组合逻辑的单个分区的仿真模型中循环。优选实施例在硬件加速器中使用特殊的4输入1输出功能单元来代替正常的锁存功能，该功能将仅存储组合的周期的旧锁存值回写。其他实施例包括针对阵列和透明锁存器的单独阵列写禁止的硬件支持，取决于该周期是仅组合周期和仅锁存周期。还包括依赖于硬件断点的发生的条件阵列写禁用，其支持从锁存器加组合周期切换到仅锁存周期，以在对锁存器发生断点时评估组合逻辑之前给予用户控制。

3. 发明申请

US20080243462A1 INSTRUCTION ENCODING IN A HARDWARE SIMULATION ACCELERATOR 有权
标题翻译：硬件仿真加速器中的指令编码
公开(公告)号：US20080243462A1
公开(公告)日：2008-10-02
申请号：US11694940
申请日：2007-03-30
申请人： Gernot E. Guenther , Viktor Gyuris , Kevin Anthony Pasnik , Thomas John Tryt , John H. Westermann
发明人： Gernot E. Guenther , Viktor Gyuris , Kevin Anthony Pasnik , Thomas John Tryt , John H. Westermann
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F11/261 , G06F17/5027
摘要： A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the method by which the hardware simulation accelerator can read encoded instructions to simulate the logic design, and computer program product of the encoded instructions to simulate a logic design in a hardware accelerator. Each instruction has one of a plurality of opcodes, the opcodes select which of the hardware resources of the hardware simulation accelerator will implement and use the values set forth in other programmable bits of the encoded instruction. The encoded instruction may be a routing and/or a gate evaluation instruction.
摘要翻译：用于模拟逻辑设计的硬件仿真加速器，用于编码在硬件仿真加速器中使用的指令的方法，以及具有硬件仿真加速器可以读取编码指令以模拟逻辑设计的方法的代码的计算机程序产品，以及计算机编码指令的程序产品来模拟硬件加速器中的逻辑设计。每个指令具有多个操作码之一，操作码选择硬件模拟加速器的硬件资源中的哪一个将实现，并使用编码指令的其他可编程位中阐述的值。编码指令可以是路由和/或门评估指令。

4. 发明授权

US07945433B2 Hardware simulation accelerator design and method that exploits a parallel structure of user models to support a larger user model size 有权
标题翻译：硬件仿真加速器设计和方法利用用户模型的并行结构来支持更大的用户模型大小
公开(公告)号：US07945433B2
公开(公告)日：2011-05-17
申请号：US11742100
申请日：2007-04-30
申请人： Daniel R. Crouse, II , Gernot E. Guenther , Viktor Gyuris , Harrell Hoffman , Kevin A. Pasnik , Thomas J. Tryt , John H. Westermann, Jr.
发明人： Daniel R. Crouse, II , Gernot E. Guenther , Viktor Gyuris , Harrell Hoffman , Kevin A. Pasnik , Thomas J. Tryt , John H. Westermann, Jr.
IPC分类号： G06F9/445 , G06F9/30
CPC分类号： G06F17/5022
摘要： A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs.
摘要翻译：一种用于设计验证的系统和方法，更具体地说，一种利用用户模型的并行结构来支持大型用户模型大小的硬件仿真加速器设计和方法。该方法包括计算机，其包括共享公共指令存储器池（IM）的N个逻辑评估单元（LEU）。计算机基础设施可操作地：在网表中划分多个并行操作; 并且从单个IM向N个LEU发送分区数量的并行操作的相同指令流。该系统是具有计算机基础设施的硬件模拟加速器，其可操作以从单个IM向多个LEU提供指令流。多个LEU与多个IM集成在一起，使得每个LEU被配置为使用来自多个IM中的任何一个的指令，从而允许相同的指令流来驱动多个LEU。

5. 发明授权

US07562320B2 Asic based conveyor belt style programmable cross-point switch hardware accelerated simulation engine 失效
标题翻译：基于Asic的输送带式可编程交叉点开关硬件加速仿真引擎
公开(公告)号：US07562320B2
公开(公告)日：2009-07-14
申请号：US11532248
申请日：2006-09-15
申请人： Gernot E. Guenther , Viktor Sandor Gyuris , Thomas J. Tryt , John H. Westerman, Jr.
发明人： Gernot E. Guenther , Viktor Sandor Gyuris , Thomas J. Tryt , John H. Westerman, Jr.
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： An ASIC based hardware accelerated simulation engine accelerates logic verification of integrated circuit designs utilizing a field of ASIC chips interconnected by direct connections. Communication between the chips has to be accomplished by switching technology internal to the chips. The switching technology employing programmable cross-point switches; i.e. hardware elements with input, output and command ports which propagate signals from the input ports to the output ports following a given permutation determined by values on the command port. The ASIC chip contains an instruction memory to program the logic elements thereof. A conveyor belt based implementation of the programmable cross-point switches provides reduced command bit requirements.
摘要翻译：基于ASIC的硬件加速仿真引擎利用通过直接连接互连的ASIC芯片领域加速了集成电路设计的逻辑验证。芯片之间的通信必须通过切换芯片内部的技术来实现。采用可编程交叉点开关的开关技术; 即具有输入，输出和命令端口的硬件元件，其根据命令端口上的值确定的给定置换将信号从输入端口传播到输出端口。 ASIC芯片包含用于对其逻辑元件进行编程的指令存储器。基于传送带的可编程交叉点开关的实现提供了减少的命令位要求。

6. 发明申请

US20080127012A1 Conveyor Belt Style Cross-Point 失效
标题翻译：输送带风格交叉点
公开(公告)号：US20080127012A1
公开(公告)日：2008-05-29
申请号：US11532248
申请日：2006-09-15
申请人： Gernot E. Guenther , Viktor Sandor Gyuris , Thomas J. Tryt , John H. Westerman
发明人： Gernot E. Guenther , Viktor Sandor Gyuris , Thomas J. Tryt , John H. Westerman
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： An ASIC based hardware accelerated simulation engine accelerates the process of logic verification of integrated circuit designs utilizing a field of ASIC chips. The ASIC chips are interconnected by direct connections, with the communication between these chips has to be accomplished by switching technology internal to the chips. The switching technology employs programmable cross-points, that is, hardware elements with input, output and command ports. The programmable cross-points propagate signals from their input ports to their output ports following a given permutation determined by the values on the command port. To program the various logic elements of ASIC chip, the ASIC chip contains an instruction memory. This invention provides a conveyor belt based implementation of the programmable cross-point that has reduced command bit requirements compared to the prior art solution.
摘要翻译：基于ASIC的硬件加速仿真引擎利用ASIC芯片领域加速了集成电路设计的逻辑验证过程。 ASIC芯片通过直接连接互连，这些芯片之间的通信必须通过芯片内部的切换技术来实现。交换技术采用可编程交叉点，即具有输入，输出和命令端口的硬件元件。可编程交叉点根据命令端口上的值确定的给定置换将信号从其输入端口传播到其输出端口。为了对ASIC芯片的各种逻辑元件进行编程，ASIC芯片包含指令存储器。本发明提供了一种基于传送带的可编程交叉点的实现，与现有技术的解决方案相比，其具有降低的命令位要求。

7. 发明申请

US20080127006A1 Real-Time Data Stream Decompressor 审中-公开
标题翻译：实时数据流解压缩器
公开(公告)号：US20080127006A1
公开(公告)日：2008-05-29
申请号：US11553605
申请日：2006-10-27
申请人： Gernot E. Guenther , Viktor S. Gyuris , Thomas J. Tryt , John H. Westermann
发明人： Gernot E. Guenther , Viktor S. Gyuris , Thomas J. Tryt , John H. Westermann
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Method, system, and program product for expanding the effective capacity of embedded memory by storing data in a compressed form and reading the data out with subsequent data decompression, including adaptive decompression and data conversion. The system and method for compression and decompression of HDL code between HDL code storage and HDL code processing for simulation of a device or system.
摘要翻译：方法，系统和程序产品，通过以压缩形式存储数据并通过随后的数据解压缩读取数据，包括自适应解压缩和数据转换，来扩展嵌入式存储器的有效容量。用于HDL代码存储和HDL代码处理之间的HDL代码的压缩和解压缩的系统和方法，用于对设备或系统进行仿真。

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