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1. 发明授权

US5260936A HDLC store and forward apparatus 失效
标题翻译： HDLC存储和转发设备
公开(公告)号：US5260936A
公开(公告)日：1993-11-09
申请号：US904084
申请日：1992-06-25
申请人： Gerard Bardet , Jean-Francois Le Pennec , Patrick Michel , Philippe Therias
发明人： Gerard Bardet , Jean-Francois Le Pennec , Patrick Michel , Philippe Therias
IPC分类号： H04L29/02 , H04L1/00 , H04L12/56 , H04L13/08 , H04L29/08 , H03M13/00
CPC分类号： H04L12/56 , H04L1/0078
摘要： A store and forward apparatus includes a deserializer for deserializing received frames of data into a sequence of n-bit words. Each frame includes a header, a data field and a frame checking sequence (FCS) generated by a first telecommunication node. The apparatus includes a storage for storing the deserialized n-bit words, and a processor for addressing the storage and for generating n-bit words corresponding to a new header of the received frame. The apparatus also includes a serializer receiving the n-bit words from the storage for generating a new frame having a new header field and a new FCS to be transmitted to a second telecommunication node. The apparatus further includes a receiver for receiving a frame and computes a first partial FCS covering the frame's data field only and a storage for storing the first partial FCS. During forwarding, n-bit words to be transmitted are simultaneously received by the serializer and by an apparatus for computing a second partial FCS covering the data field only. At the end of the serialization process, the two partial FCS results are compared to detect an error occurring during the computing of the new header of the frame. The result of the comparison is used as a control signal for altering the value of the FCS computed by serializer prior to transmission.

2. 发明授权

US5043989A Terminal adapter having a multiple HDLC communication channels receiver for processing control network management frames 失效
标题翻译：具有用于处理控制网络管理帧的多个HDLC通信信道接收机的终端适配器
公开(公告)号：US5043989A
公开(公告)日：1991-08-27
申请号：US401892
申请日：1989-09-01
申请人： Philippe Dalmas , Daniel Esteban , Jean-Francois Le Pennec , Patrick Michel , Philippe Therias
发明人： Philippe Dalmas , Daniel Esteban , Jean-Francois Le Pennec , Patrick Michel , Philippe Therias
IPC分类号： H04L29/04 , H04L1/00 , H04L29/06 , H04L29/08
CPC分类号： H04L29/06 , H04L1/0045 , H04L1/0061 , H04L69/324
摘要： A terminal adapter for a telecommunication network having a receiver for multiple HDLC communication channels. The receiver includes a BCC calculator for computing and checking the validity of a received HDLC CNM frame. The terminal adapter further includes a device for detecting the reception of a specific CNM header included in a CNM frame on any of the HDLC communication channels and responsive to the detection for setting the BCC calculator to a predefined state. The latter state corresponds to the state of the BCC calculator after a computation of BCC for the specific CNM header. Therefore the BCC calculator can proceed with computation of said BCC for the CNM frame.

3. 发明授权

US06999994B1 Hardware device for processing the tasks of an algorithm in parallel 失效
标题翻译：用于并行处理算法任务的硬件设备
公开(公告)号：US06999994B1
公开(公告)日：2006-02-14
申请号：US09606899
申请日：2000-06-29
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F15/16 , G06F9/46
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units.
摘要翻译：一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联定义为一个过程或一个决策或一个过程以及以下决定。任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作。

4. 发明授权

US06725302B1 Universal serial bus (USB) with wireless communication hubs 有权
标题翻译：通用串行总线（USB），带无线通信集线器
公开(公告)号：US06725302B1
公开(公告)日：2004-04-20
申请号：US09656583
申请日：2000-09-06
申请人： Alain Benayoun , Jean-Francois Le Pennec , Andre Albano , Patrick Michel
发明人： Alain Benayoun , Jean-Francois Le Pennec , Andre Albano , Patrick Michel
IPC分类号： G06F1314
CPC分类号： G06F13/385 , G06F13/4045 , G06F2213/3814 , G06F2213/4002
摘要： The invention relates to a Universal Serial Bus (USB) with two wireless communication hubs (USB hubs). One of these hubs is connected to a first host computer, and both USB hubs are connected to a plurality of I/O devices. Each USB hub includes a wireless adapter and an antenna connected to the wireless adapter. The wireless adapter of each USB hub comprises a transmitting/receiving unit for transmitting data via the antenna to the wireless adapter of the other USB hub or receiving data via the antenna from the wireless adapter of the other USB hub. The wireless adapter also comprises a wireless dual port, which is automatically configured upstream or downstream when the first host computer is connected to one of the USB hubs.
摘要翻译：本发明涉及具有两个无线通信集线器（USB集线器）的通用串行总线（USB）。这些集线器中的一个连接到第一主机，并且两个USB集线器连接到多个I / O设备。每个USB集线器包括无线适配器和连接到无线适配器的天线。每个USB集线器的无线适配器包括用于经由天线将数据发送到另一个USB集线器的无线适配器的发送/接收单元，或者通过另一USB集线器的无线适配器经天线接收数据。无线适配器还包括无线双端口，其在第一主机连接到其中一个USB集线器时被自动配置为上游或下游。

5. 发明授权

US06675291B1 Hardware device for parallel processing of any instruction within a set of instructions 有权
标题翻译：用于并行处理一组指令内的任何指令的硬件设备
公开(公告)号：US06675291B1
公开(公告)日：2004-01-06
申请号：US09558792
申请日：2000-04-26
申请人： Alain Benayoun , Jean-Francois Le Pennec , Claude Pin , Patrick Michel
发明人： Alain Benayoun , Jean-Francois Le Pennec , Claude Pin , Patrick Michel
IPC分类号： G06F944
CPC分类号： G06F9/38 , G06F9/30145 , G06F9/3822
摘要： Hardware device for parallel processing a determined instruction of a set of instructions having a same format defining operand fields and other data fields, the execution of this determined instruction being represented as an algorithm comprising a plurality of processes, the processing of which depending on decisions. Such a device comprises means (22-30) for activating the processing of one or several processes (32-38) determined by the operand fields of the instruction, decision macroblocks (12-20) each being associated with a specific instruction of the set of instructions, only one decision marcoblock being selected by the determined instruction in order to determine which are the process(es) to be activated for executing the determined instruction.
摘要翻译：用于并行处理具有定义操作数字段和其他数据字段的相同格式的一组指令的确定指令的硬件设备，该确定的指令的执行被表示为包括多个处理的算法，其根据决定进行处理。这种设备包括用于激活由指令的操作数字段确定的一个或几个处理（32-38）的处理的装置（22-30），每个与组的特定指令相关联的决策宏块（12-20）的指令，所确定的指令仅选择一个决策marcoblock，以便确定哪些是要激活的进程来执行所确定的指令。

6. 发明授权

US06341132B1 ATM node having local error correcting procedures 失效
标题翻译： ATM节点具有本地纠错程序
公开(公告)号：US06341132B1
公开(公告)日：2002-01-22
申请号：US09018742
申请日：1998-02-04
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Gilles Toubol
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Gilles Toubol
IPC分类号： H04L1256
CPC分类号： H04Q11/0478 , H04L2012/5647 , H04L2012/5652
摘要： A telecommunication node for an Asynchronous Transfer Mode (ATM) telecommunication network performs Segmentation and Reassembly (SAR) of ATM cells. The SAR particularly provides Virtual Channel Identifier (VCI) and Virtual Path Identifier (VPI) translation and further provides a Direct Memory Access (DMA) for accessing an external storage. When the VCI and VPI identifiers are representative of an Error Code Correcting (ECC) procedure to be carried out in the local mode, the SAR circuit performs a first DMA access which is decoded by an address decoder. Conversely, when no ECC procedure is locally required, the SAR decodes the VCI and VPI and performs a second DMA access which is also decoded by the address decoder. The latter decoding is then used by a Reed-Solomon Coder and Decoder for possibly performing an error correcting procedure on the ATM message formed by the ATM cells being processed.
摘要翻译：用于异步传输模式（ATM）电信网络的电信节点执行ATM信元的分段和重组（SAR）。 SAR特别提供虚拟信道标识符（VCI）和虚拟路径标识符（VPI）转换，并进一步提供用于访问外部存储器的直接存储器访问（DMA）。当VCI和VPI标识符代表在本地模式下执行的错误代码校正（ECC）过程时，SAR电路执行由地址解码器解码的第一DMA访问。相反，当本地不需要ECC过程时，SAR对VCI和VPI进行解码，并执行也被地址解码器解码的第二DMA访问。后来的解码然后由Reed-Solomon编码器和解码器用于可能对正被处理的ATM信元形成的ATM信息执行纠错过程。

7. 发明授权

US6067381A Method of reinitializing dictionaries in a data transmission system using data compression 失效
标题翻译：使用数据压缩在数据传输系统中重新初始化字典的方法
公开(公告)号：US6067381A
公开(公告)日：2000-05-23
申请号：US67457
申请日：1998-04-28
申请人： Alain Benayoun , Patrick Michel , Jacques Fieschi , Jean-Francois Le Pennec
发明人： Alain Benayoun , Patrick Michel , Jacques Fieschi , Jean-Francois Le Pennec
IPC分类号： H03M7/30 , G06K9/36 , H03M7/34
CPC分类号： H03M7/3088
摘要： Method of reinitializing dictionaries in a data transmission system using data compression having a transmit device and a receive device, and in which strings of characters have to be transmitted in a compressed form, the transmit device having a transmit dictionary storing codewords associated with the strings of characters which are transmitted instead of the strings of characters, the receive device having a receive dictionary storing codewords associated with the strings of characters, and both dictionaries being updated each time a new string of characters has to be transmitted so that the contents of the dictionaries remain identical. This method saves at least the addresses of the parts of the transmit or receive dictionary which have to be modified by a dictionary updating operation, builds a check message based upon the contents of the transmit dictionary updated by the dictionary updating operation, transmits the check message from the transmit device to the receive device, and then deletes in both dictionaries the parts which are determined by the saved addresses in the event that the check message does not correspond to the contents of the updated receive dictionary. This enables both dictionaries to be reinitialized in an intermediate state without being reset.
摘要翻译：在使用具有发送设备和接收设备的数据压缩的数据传输系统中重新初始化字典的方法，并且其中字符串必须以压缩形式发送，所述发送设备具有存储与字符串相关联的码字的发送字典发送而不是字符串的字符，接收装置具有存储与字符串相关联的码字的接收字典，并且每当必须发送新的字符串字符时，两个字典都被更新，使得字典的内容保持相同该方法至少存储必须通过字典更新操作修改的发送或接收字典的部分的地址，基于由字典更新操作更新的发送字典的内容构建检查消息，发送检查消息从发送设备到接收设备，然后在两个字典中删除在检查消息不对应于更新的接收字典的内容的情况下由保存的地址确定的部分。这使得两个字典都不会被重新初始化在中间状态。

8. 发明授权

US5790608A Apparatus and method for synchronizing clock signals for digital links in a packet switching mode 失效
标题翻译：用于在分组交换模式下同步用于数字链路的时钟信号的装置和方法
公开(公告)号：US5790608A
公开(公告)日：1998-08-04
申请号：US574840
申请日：1995-12-19
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Joaquin Picon
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Joaquin Picon
IPC分类号： H04J3/06 , H04L12/70 , H04Q11/04 , H04L7/00
CPC分类号： H04Q11/0478 , H04J3/0632 , H04J3/0658 , H04L2012/5615 , H04L2012/5616 , H04L2012/5674 , Y10S370/902
摘要： An apparatus and a method to synchronize the clock signal of a first (or slave) data terminal equipment A (240-1) to a second (or master) data terminal equipment B (240-2) connected to a communication network (10) through respectively a first network node (51) and a second network node (52). The communication network has a reference clock that it transmits to the second network node which compares it with the clock signal that it receives from the second data terminal equipment. The phase difference is then detected and converted into a frame which may be an ATM cell or any other frames so that it can be switched with the data frames sent by the second DTE and transmitted to the first DTE through the communication network. The frame containing the phase difference has a specific header so that it can be distinguished from the other transmitted data frames. The first network node receives the frames, detects the phase difference frame and decodes it before it is sent to a digital to analog converter. This later generates then an analog signal which adjusts the phase of the reference clock that the first network node has extracted from the communication network. The adjusted clock signal is transmitted to the first DTE which is therefore synchronized with the second (or master) DTE.
摘要翻译：将第一（或从属）数据终端设备A（240-1）的时钟信号与连接到通信网络（10）的第二（或主））数据终端设备B（240-2）同步的装置和方法，分别通过第一网络节点（51）和第二网络节点（52）。通信网络具有它向第二网络节点发送的参考时钟，该第二网络节点与从第二数据终端设备接收的时钟信号进行比较。然后检测相位差并将其转换成可以是ATM信元或任何其他帧的帧，使得其可以与由第二DTE发送的数据帧进行切换，并通过通信网络发送到第一DTE。包含相位差的帧具有特定头部，使得其可以与其他发送的数据帧区分开。第一网络节点接收帧，检测相位差帧并将其解码，然后发送到数模转换器。这随后产生一个模拟信号，该模拟信号调节第一网络节点从通信网络提取的参考时钟的相位。经调整的时钟信号被发送到第一DTE，因此第一DTE与第二（或主）DTE同步。

9. 发明授权

US5751714A Time division multiplex frame slot assignment system and method for interconnecting telephone stations on a token ring network 失效
标题翻译：时分复用帧时隙分配系统和方法，用于在令牌环网上互连电话台
公开(公告)号：US5751714A
公开(公告)日：1998-05-12
申请号：US727333
申请日：1996-10-08
申请人： Andre Albano , Rene Chuniaud , Jacques Fieschi , Patrick Michel , Jean-Francois Le Pennec
发明人： Andre Albano , Rene Chuniaud , Jacques Fieschi , Patrick Michel , Jean-Francois Le Pennec
IPC分类号： H04L12/43 , H04L12/433 , H04J3/12
CPC分类号： H04L12/433 , H04L12/43
摘要： In a token ring network a periodic recirculating frame having a plurality of information carrying slots and a header section is used for enabling a plurality of telephone stations to exchange information carrying signals. The header is provided with a token which can assume one of three states. In the first state FF, a telephone station wanting to make a call, changes the token to the second state 00 and inserts call establishment information in the header. A server station also connected in the ring detects the second state as a request to establish a connection from and to a station specified in the header. The server changes the token to the third state AA and inserts a slot assignment in the header. All stations receiving a frame with a token in the third state examine the header. The calling station implies confirmation of the requested connection and the called station is made aware of the call and the identity of the caller. When this frame returns to the server the token state is set to FF and another station on the ring can request a slot for communication with another station.
摘要翻译：在令牌环网络中，使用具有多个信息携带时隙的周期性再循环帧和报头部分，以使多个电话台能够交换信息携带信号。标题提供有一个可以承担三种状态之一的令牌。在第一状态FF中，要进行呼叫的电话台将令牌改变为第二状态00，并将呼叫建立信息插入到头部中。还连接在环中的服务器站检测到第二状态，作为与头中指定的站建立连接的请求。服务器将令牌更改为第三个状态AA，并在标题中插入一个插槽分配。接收具有第三状态的令牌的帧的所有站检查标题。呼叫站意味着确认所请求的连接，并且使被叫站知道呼叫和呼叫者的身份。当该帧返回到服务器时，令牌状态被设置为FF，并且环上的另一个站可以请求与另一站通信的时隙。

10. 发明授权

US08635620B2 Hardware device for processing the tasks of an algorithm in parallel 失效
标题翻译：用于并行处理算法任务的硬件设备
公开(公告)号：US08635620B2
公开(公告)日：2014-01-21
申请号：US13365360
申请日：2012-02-03
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F9/46 , G06F15/76 , G06F7/38
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.
摘要翻译：一种硬件设备，用于同时处理与包括多个进程的算法相关联的一组固定的预定任务，其中一些进程取决于二进制决策，包括用于处理数据，作出决定和/或处理数据的多个任务单元并作出决定，包括源任务单位和目标任务单位。任务互连逻辑意味着将任务单元互连以将来自源任务单元的动作传送到目的地任务单元。每个任务单元包括处理器，用于响应于接收到的请求动作仅执行与算法相关联的固定的一组预定任务的特定单个任务，以及状态管理器，用于处理源任务单元的动作并构建要发送到目标任务单元的动作。

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